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the following document contains information on sp ansion memory products. although the doc-ument is marked with the name of the company that orig inally developed the specification, spansion will continue to offer these products to existing customers. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansion product. any changes that have been made are the result of no rmal data sheet improvement and are noted in the document revision summary, where supported . future routine re visions will occur when appro-priate, and changes will be noted in a revision summary. continuity of ordering part numbers spansion continues to support existing part number s beginning with ?am? and ?mbm?. to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local sales office for additi onal information about spansion memory solutions. am29bdd160g data sheet publication number 24960 revision d amendment 5 issue date june 7, 2006 for new designs, s29cd016g supersedes am29bdd 160g and is the factory-recommended migration path for this device. please refer to the s29cd016g datasheet for specifications and ordering infor- mation.
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data sheet publication# 24960 rev: d amendment: 5 issue date: june 7, 2006 refer to amd?s website (www.amd.com) for the latest information. am29bdd160g 16 megabit (1 m x 16-bit/512 k x 32-bi t), cmos 2.5 volt-only burst mode, dual boot, simultaneous read/write flash memory distinctive characteristics architectural advantages ? simultaneous read/write operations ? data can be continuously read from one bank while executing erase/program functions in other bank. (?40c to 85c, 56 mhz and below only) ? zero latency between read and write operations ? two bank architecture: 75%/25% ? user-defined x16 or x32 data bus ? dual boot block ? top and bottom boot in the same device ? flexible sector architecture ? eight 8 kbytes, thirty 64 kbytes, and eight 8 kbytes sectors ? manufactured on 0.17 m process technology ? secsi (secured silicon) sector (256 bytes) ? current version of device has 64 kbytes; future versions will have 256 bytes ? factory locked and identifiable: 16 bytes for secure, random factory electronic se rial number; remainder may be customer data programmed by amd ? customer lockable: can be read, programmed, or erased just like other se ctors. once locked, data cannot be changed ? programmable burst interface ? interface to any high performance processor ? modes of burst read operation: linear burst: 4 double words (x32), 8 words (x16) and double words (x32), and 32 words (x16) with wrap around ? single power supply operation ? optimized for 2.5 to 2.75 volt read, erase, and program operations ? compatible with jedec standards (jc42.4) ? pinout and software compatible with single-power-supply flash standard performance characteristics ? high performance read access ? initial/random access time as fast as 54 ns ? burst access time as fast as 9 ns for ball grid array package ? ultra low power consumption ? burst mode read: 90 ma @ 66 mhz max ? program/erase: 50 ma max ? standby mode: cmos: 60 a max ? minimum 1 million write cycles guaranteed per sector ? 20 year data retention at 125c ? versatilei/o tm control ? device generates data output voltages and tolerates data input voltages as determined by the voltage on the v io pin ? 1.65 v to 2.75 v compatible i/o signals software features ? persistent sector protection ? a command sector protection method to lock combinations of individual sectors and sector groups to prevent program or eras e operations within that sector (requires only v cc levels) ? password sector protection ? a sophisticated sector prot ection method to lock combinations of individual sectors and sector groups to prevent program or eras e operations within that sector using a user-definable 64-bit password ? supports common flash interface (cfi) ? unlock bypass program command ? reduces overall programming time when issuing multiple program command sequences ? data# polling and toggle bits ? provides a software meth od of detecting program or erase operation completion hardware features ? program suspend/resume & erase suspend/resume ? suspends program or erase operations to allow reading, programming, or erasing in same bank ? hardware reset (reset#), ready/busy# (ry/by#), and write protect (wp#) inputs ? acc input ? accelerates programming time for higher throughput during system production ? package options ? 80-pin pqfp ? 80-ball fortified bga note: for new designs, s29cd016g supersedes am29bdd160g and is the factory-recommended migration path for this device. please r efer to the s29cd016g datasheet for specifica- tions and ordering information.
2 am29bdd160g june 7, 2006 general de s cription the am2 9 bdd160 is a 16 meg abi t, 2 . 5 volt-only si n- gle power su pply bu r s t mode fl as h memory dev i ce . the dev i ce c a n b e conf i g u red for e i ther 1,04 8 ,576 word s i n 16- bi t mode or 524,2 88 do ub le word s i n 3 2- bi t mode . the dev i ce c a n a l s o b e progr a mmed i n s t a nd a rd eprom progr a mmer s. the dev i ce offer s a conf i g u r ab le bu r s t i nterf a ce to 16/ 3 2- bi t m i croproce s - s or s a nd m i crocontroller s. to e l i m i n a te bus content i on, e a ch dev i ce h as s ep a r a te ch i p en ab le (ce#), wr i te en ab le (we#) a nd o u tp u t en- ab le (oe#) control s. add i t i on a l control i np u t s a re re- qui red for s ynchrono us bu r s t oper a t i on s: lo a d b u r s t addre ss v a l i d (adv#), a nd clock (clk) . e a ch dev i ce re qui re s only a si n g le 2 . 5 or 2 . 6 volt power s upply (2 . 5 v to 2 . 75 v) for b oth re a d a nd wr i te f u nct i on s. a 12 . 0-volt v pp is not re qui red for progr a m or er as e oper a t i on s , a ltho u gh a n a cceler a t i on p i n is a v ai l ab le i f f as ter progr a mm i ng perform a nce is re- qui red . the dev i ce is ent i rely comm a nd s et comp a t ib le w i th the jedec si n g le-power- s upply fla s h s tandard . the s oftw a re comm a nd s et is comp a t ib le w i th the comm a nd s et s of the 5 v am2 9 f a nd 3 v am2 9 lv fl as h f a m i l i e s. comm a nd s a re wr i tten to the comm a nd reg is ter usi ng s t a nd a rd m i croproce ss or wr i te t i m i ng . reg is ter content s s erve as i np u t s to a n i ntern a l s t a te-m a ch i ne th a t control s the er as e a nd progr a m- m i ng c i rc ui try . wr i te cycle s a l s o i ntern a lly l a tch a d- dre ss e s a nd d a t a needed for the progr a mm i ng a nd er as e oper a t i on s. re a d i ng d a t a o u t of the dev i ce is si m i l a r to re a d i ng from other fl as h or eprom de- v i ce s. the unlock bypa ss mode f a c i l i t a te s f as ter progr a m- m i ng t i me s b y re qui r i ng only two wr i te cycle s to pro- gr a m d a t a i n s te a d of fo u r . the si multaneou s read/wr i te arch i tecture prov i de s si m u lt a neo us oper a t i on b y d i v i d i ng the memory s p a ce i nto two ba nk s. the dev i ce c a n b eg i n progr a mm i ng or er asi ng i n one ba nk, a nd then si m u lt a neo us ly re a d from the other ba nk, w i th zero l a tency . th is rele as e s the s y s tem from w ai t i ng for the complet i on of progr a m or er as e oper a t i on s. s ee si m u lt a neo us re a d/wr i te oper a t i on s overv i ew a nd re s tr i ct i on s on p a ge 1 3. the dev i ce prov i de s a 256- b yte s ec si ? ( s ecured si l i con) s ector w i th a n one-t i me-progr a mm ab le (otp) mech a n is m . in a dd i t i on, the dev i ce fe a t u re s s ever a l level s of s ector protect i on, wh i ch c a n d isab le b oth the progr a m a nd er as e oper a t i on s i n cert ai n s ector s or s ector gro u p s: per sis tent s ector protect i on is a comm a nd s ector protect i on method th a t repl a ce s the old 12 v con- trolled protect i on method ; pa ss word s ector protec- t i on is a h i ghly s oph is t i c a ted protect i on method th a t re qui re s a p ass word b efore ch a nge s to cert ai n s ector s or s ector gro u p s a re perm i tted ; wp# hardware pro- tect i on prevent s progr a m or er as e i n the two o u ter- mo s t 8 k b yte s s ector s of the l a rger ba nk . the dev i ce def au lt s to the per sis tent s ector protect i on mode . the c us tomer m us t then choo s e i f the s t a nd a rd or p ass word protect i on method is mo s t de si r ab le . the wp# h a rdw a re protect i on fe a t u re is a lw a y s a v ai l ab le, i ndependent of the other protect i on method cho s en . the ver s at i lei/o? (v ccq ) fe a t u re a llow s the o u tp u t volt a ge gener a ted on the dev i ce to b e determ i ned bas ed on the v io level . th is fe a t u re a llow s th is dev i ce to oper a te i n the 1 .8 v i/o env i ronment, dr i v i ng a nd re- ce i v i ng si gn a l s to a nd from other 1 .8 v dev i ce s on the sa me bus. in a dd i t i on, i np u t s a nd i/o s th a t a re dr i ven extern a lly a re c a p ab le of h a ndl i ng 3. 6 v . the ho s t s y s tem c a n detect whether a progr a m or er as e oper a t i on is complete b y o bs erv i ng the ry/by# p i n, b y re a d i ng the dq7 (d a t a # poll i ng), or dq6 (tog- gle) s tatu s b i t s . after a progr a m or er as e cycle h as b een completed, the dev i ce is re a dy to re a d a rr a y d a t a or a ccept a nother comm a nd . the s ector era s e arch i tecture a llow s memory s ec- tor s to b e er as ed a nd reprogr a mmed w i tho u t a ffect i ng the d a t a content s of other s ector s. the dev i ce is f u lly er as ed when s h i pped from the f a ctory . hardware data protect i on me asu re s i ncl u de a low v cc detector th a t au tom a t i c a lly i nh ibi t s wr i te oper a - t i on s d u r i ng power tr a n si t i on s. the pa ss word and s oftware s ector protect i on fe a t u re d isab le s b oth progr a m a nd er as e oper a t i on s i n a ny com bi n a t i on of s ector s of memory . th is c a n b e a ch i eved i n- s y s tem a t v cc level . the pro g ram/era s e s u s pend/era s e re s ume fe a - t u re en ab le s the us er to p u t er as e on hold for a ny pe- r i od of t i me to re a d d a t a from, or progr a m d a t a to, a ny s ector th a t is not s elected for er asu re . tr u e ba ck- gro u nd er as e c a n th us b e a ch i eved . the hardware re s et# p i n term i n a te s a ny oper a t i on i n progre ss a nd re s et s the i ntern a l s t a te m a ch i ne to re a d i ng a rr a y d a t a. the dev i ce offer s two power- sa v i ng fe a t u re s. when a ddre ss e s h a ve b een s t ab le for a s pec i f i ed a mo u nt of t i me, the dev i ce enter s the automat i c s leep mode . the s y s tem c a n a l s o pl a ce the dev i ce i nto the s tandby mode . power con su mpt i on is gre a tly re- d u ced i n b oth the s e mode s. amd? s fl as h technology com bi ne s ye a r s of fl as h memory m a n u f a ct u r i ng exper i ence to prod u ce the h i ghe s t level s of qua l i ty, rel iabi l i ty a nd co s t effect i ve- ne ss. the dev i ce electr i c a lly er as e s a ll bi t s w i th i n a s ector si m u lt a neo us ly v ia fowler-nordhe i m t u nnell i ng . the d a t a is progr a mmed usi ng hot electron i n j ect i on .
june 7, 2006 am29bdd160g 3 table of content s product s elector gu i de . . . . . . . . . . . . . . . . . . . . . 5 block d i a g ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 block d i a g ram of si multaneou s operat i on c i rcu i t . . . . . . . . . . . . . 6 connect i on d i a g ram . . . . . . . . . . . . . . . . . . . . . . . . 7 special package handling instructions .................................... 8 p i n conf ig urat i on . . . . . . . . . . . . . . . . . . . . . . . . . . 9 lo gi c s ymbol s . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 x16 mode .................................................................................. 9 x32 mode .................................................................................. 9 order i n g informat i on . . . . . . . . . . . . . . . . . . . . . . 10 dev i ce bu s operat i on s . . . . . . . . . . . . . . . . . . . . . 11 table 1. device bus operation .......................................................12 versatilei/o? (v io ) control .................................................... 13 requirements for reading array data ................................... 13 simultaneous read/write operations overview and restrictions ................................... 13 overview ............................................................................. 13 restrictions .......................................................................... 13 table 2. bank assignment for boot bank sector devices ................................................................................13 simultaneous read/write operations with zero latency ...... 13 table 3. top boot bank select .......................................................14 table 4. bottom boot bank select ..................................................14 writing commands/command sequences ............................ 14 accelerated program and erase operations ....................... 14 autoselect functions ........................................................... 14 automatic sleep mode (asm) ................................................ 14 reset#: hardware reset pin ............................................... 15 output disable mode .............................................................. 15 autoselect mode ..................................................................... 15 table 5. am29bdd160 autoselect codes (high voltage method) .16 asynchronous read operation (non-burst) ........................... 16 figure 1. asynchronous read operation........................................ 16 synchronous (burst) read operation .................................... 17 linear burst read operations ................................................ 17 table 6. 16-bit and 32-bit linear and burst data order .................17 ce# control in linear mode ................................................ 18 adv# control in linear mode .............................................. 18 reset# control in linear mode ......................................... 18 oe# control in linear mode ................................................ 18 ind/wait# operation in linear mode ................................. 18 table 7. valid configuration register bit definition for ind/wait# 20 figure 2. end of burst indicator (ind/wait#) timing for linear 8-word burst operation............................................................................... 20 burst access timing control ............................................... 21 initial burst access delay control ....................................... 21 table 8. burst initial access delay ..................................................21 figure 3. initial burst delay control ................................................ 21 configuration register ............................................................ 22 table 9. configuration register definitions .....................................22 table 10. configuration register after device reset .....................24 initial access delay configuration .......................................... 24 s ector protect i on . . . . . . . . . . . . . . . . . . . . . . . . 24 persistent sector protection ................................................... 24 persistent protection bit (ppb) ............................................ 25 persistent protection bit lock (ppb lock) .......................... 25 dynamic protection bit (dyb) ............................................. 25 table 11. sector protection schemes ............................................ 26 persistent sector protection mode locking bit ....................... 26 password protection mode ..................................................... 26 password and password mode locking bit ............................ 26 64-bit password ................................................................... 27 write protect (wp#) ................................................................ 27 secsi? (secured silicon) sector protection .......................... 27 secsi sector protection bit ..................................................... 28 persistent protection bit lock ................................................. 28 hardware data protection ...................................................... 28 low v cc write inhibit ........................................................... 28 write pulse glitch protection ............................................ 28 logical inhibit ....................................................................... 28 power-up write inhibit ......................................................... 28 v cc and v io power-up and power-down sequencing ......... 28 table 12. sector addresses for top boot sector devices ............. 29 table 13. sector addresses for bottom boot sector devices ........ 30 table 14. cfi query identification string ....................................... 31 table 15. cfi system interface string ........................................... 31 table 16. cfi device geometry definition ..................................... 32 table 17. cfi primary vendor-specific extended query ............... 32 command def i n i t i on s . . . . . . . . . . . . . . . . . . . . . 3 4 reading array data in non-burst mode .................................. 34 reading array data in burst mode ......................................... 34 read/reset command ........................................................... 34 autoselect command ............................................................. 35 program command sequence ............................................... 35 accelerated program command ............................................ 35 unlock bypass command sequence ..................................... 35 figure 4. program operation ......................................................... 36 unlock bypass entry command .......................................... 36 unlock bypass program command .................................... 36 unlock bypass chip erase command ................................ 36 unlock bypass cfi command ............................................ 36 unlock bypass reset command ......................................... 37 chip erase command ............................................................ 37 sector erase command ......................................................... 37 figure 5. erase operation.............................................................. 38 sector erase and program suspend command .................... 38 sector erase and program suspend operation mechanics ... 38 table 18. allowed operations during erase/program suspend ... 38 sector erase and program resume command ..................... 39 configuration register read command ................................. 39 configuration register write command ................................. 39 common flash interface (cfi) command .............................. 39 secsi sector entry command ................................................ 41 password program command ................................................ 41 password verify command .................................................... 41 password protection mode locking bit program command .. 42 persistent sector protection mode locking bit program com- mand ....................................................................................... 42 secsi sector protection bit program command .................... 42 ppb lock bit set command ................................................... 42 dyb write command ............................................................. 42 password unlock command .................................................. 42 ppb program command ........................................................ 43
4 am29bdd160g june 7, 2006 all ppb erase command ....................................................... 43 dyb write ............................................................................... 43 ppb lock bit set .................................................................... 43 dyb status ............................................................................. 43 ppb status ............................................................................. 44 ppb lock bit status ............................................................... 44 non-volatile protection bit program and erase flow ............. 44 table 19. memory array command definitions (x32 mode) ...........45 table 20. sector protection command definitions (x32 mode) ......46 table 21. memory array command definitions (x16 mode) ...........47 table 22. sector protection command definitions (x16 mode) ......48 dq7: data# polling ................................................................. 49 ry/by#: ready/busy# ........................................................... 49 figure 6. data# polling algorithm ................................................... 50 dq6: toggle bit i .................................................................... 50 dq2: toggle bit ii ................................................................... 50 reading toggle bits dq6/dq2 .............................................. 51 dq5: exceeded timing limits ................................................ 51 figure 7. toggle bit algorithm......................................................... 51 dq3: sector erase timer ....................................................... 52 table 23. write operation status ....................................................52 figure 8. maximum negative overshoot waveform ....................... 53 figure 9. maximum positive overshoot waveform......................... 53 dc character is t i c s . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 10. i cc1 current vs. time (showing active and automatic sleep currents) ......................................................................................... 55 figure 11. typical i cc1 vs. frequency............................................. 55 te s t cond i t i on s . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 12. test setup...................................................................... 56 table 24. test specifications ..........................................................56 key to s w i tch i n g waveform s . . . . . . . . . . . . . . . 56 s w i tch i n g waveform s . . . . . . . . . . . . . . . . . . . . . 56 figure 13. input waveforms and measurement levels ................. 56 ac character is t i c s . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 14. vcc and vio power-up diagram ................................. 57 figure 15. conventional read operations timings ....................... 60 figure 16. burst mode read (x32 mode)....................................... 60 figure 17. asynchronous command write timing ........................ 61 figure 18. synchronous command write/read timing................. 61 figure 19. reset# timings .......................................................... 63 figure 20. wp# timing .................................................................. 63 figure 21. program operation timings.......................................... 65 figure 22. chip/sector erase operation timings .......................... 66 figure 23. back-to-back cycle timings ......................................... 66 figure 24. data# polling timings (during embedded algorithms). 67 figure 25. toggle bit timings (during embedded algorithms)...... 67 figure 26. dq2 vs. dq6 for erase and erase suspend operations... 68 figure 27. synchronous data polling timing/toggle bit timings .. 68 figure 28. sector protect/unprotect timing diagram .................... 69 figure 29. alternate ce# controlled write operation timings ...... 71 era s e and pro g ramm i n g performance . . . . . . . 72 latchup character is t i c s . . . . . . . . . . . . . . . . . . . 72 pqfp and fort i f i ed bga p i n capac i tance . . . . . 72 data retent i on . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 phy si cal d i men si on s . . . . . . . . . . . . . . . . . . . . . . 7 3 pqr080C80-lead plastic quad flat package ....................... 73 laa 080C80-ball fortified ball grid array (13 x 11 mm) ......... 74 rev isi on s ummary . . . . . . . . . . . . . . . . . . . . . . . . 75
june 7, 2006 am29bdd160g 5 product selector guide note: the 54d, 64c, and 65a speed options are tested and guarant eed to operate only at the 66 mhz, 56mhz, and 40mhz frequencies respectively. operation and other frequencies is not warranted. block diagram part number am29bdd160g standard voltage range: v cc = 2.5 ? 2.75 v synchronous/burst or asynchronous speed option (clock rate) 54d (66 mhz) 64c (56 mhz) 65a (40 mhz) max initial/asynchronous access time, ns (t acc ) 54 64 67 max burst access delay (ns) 9 fbga/9.5 pqfp 10 fbga/10 pqfp 17 max clock rate (mhz) 66 56 40 min initial clock delay (clock cycles) 3 3 2 max ce# access, ns (t ce ) 58 69 71 max oe# access, ns (t oe ) 20 28 input/output buffers x-decoder y-decoder chip enable output enable logic erase voltage generator pgm voltage generator timer v cc detector state control command register v cc v ss we# reset# acc wp# word# ce# oe# dq0 ? dq15 a0?a18 data latch y-gating cell matrix address latch dq0?dq31 a0?a18 rdy buffer rdy burst state control burst address counter adv# clk a0?a20 v io ind/ wait#
6 am29bdd160g june 7, 2006 block diagram of s imultaneou s operation circuit v cc v ss upper b a nk addre ss a0?a1 8 re s et# we# ce# adv# dq0?dq 3 1 s tate control & command regi s ter upper b a nk x-decoder y-decoder l a tche s a nd control log i c oe# dq0?dq 3 1 lower b a nk y-decoder x-decoder l a tche s a nd control log i c lower b a nk addre ss s t a t us control a0?a1 8 a0?a1 8 a0?a1 8 a0?a1 8 dq0?dq 3 1 dq0?dq 3 1 16/ 3 2#
june 7, 2006 am29bdd160g 7 connection diagram 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 1 9 20 21 22 23 24 dq16 dq17 dq18 dq1 9 v ccq v ss dq20 dq21 dq22 dq23 dq24 dq25 dq26 dq27 v ccq v ss dq28 dq2 9 dq30 dq31 a - 1 a0 a1 a2 dq15 dq14 dq13 dq12 v ss v ccq dq11 dq10 dq 9 dq8 dq7 dq6 dq5 dq4 v ss v ccq dq3 dq2 dq1 dq0 nc a18 a17 a16 80 7 9 78 77 76 75 74 73 72 71 70 6 9 68 67 66 65 word# ind/wait# nc wp# we# oe# ce# v cc nc v ss adv# ry/by# nc clk reset# v ccq a3 a4 a5 a6 a7 a8 v ss acc v cc a 9 a10 a11 a12 a13 a14 a15 25 64 63 62 61 60 5 9 58 57 56 55 54 53 52 51 50 4 9 48 47 46 45 44 43 42 41 26 27 28 2 9 30 31 32 33 34 35 36 37 38 3 9 40 80-pin pqfp
8 am29bdd160g june 7, 2006 connection diagram s s pec i al packa g e handl i n g in s truct i on s s pec ia l h a ndl i ng is re qui red for fl as h memory prod- u ct s i n molded p a ck a ge s (bga) . the p a ck a ge a nd/or d a t a i ntegr i ty m a y b e comprom is ed i f the p a ck a ge b ody is expo s ed to temper a t u re s ab ove 150c for pro- longed per i od s of t i me . 8 0-ball fort i f i ed bga b 3 c 3 d 3 e 3 f 3 g 3 h 3 b4 c4 d4 e4 f4 g4 h4 b5 c5 d5 e5 f5 g5 h5 b6 c6 d6 e6 f6 g6 h6 b7 c7 d7 e7 f7 g7 h7 b 8 c 8 d 8 e 8 f 8 g 8 h 8 dq20 v ccq v ss v ccq dq2 9 a0 a1 dq1 8 dq2 3 dq24 dq26 dq 3 0 a - 1 a4 dq1 9 dq21 dq25 dq2 8 dq 3 1 a7 a5 dq17 dq22 ry/by# dq27 nc nc a 8 wp# dq 9 dq5 dq1 nc a10 a 9 dq11 dq10 dq6 dq2 nc a11 a12 a 3 a4 a5 a6 a7 a 8 a2 a 3 a6 v ss acc v cc b2 c2 d2 e2 f2 g2 h2 dq12 dq 8 dq7 dq4 dq0 a1 8 a1 3 a2 a14 b1 c1 d1 e1 f1 g1 h1 dq1 3 j 3 j4 j5 j6 j7 j 8 dq16 ind/wait# oe# ce# nc adv# j2 dq14 j1 dq15 k 3 k4 k5 k6 k7 k 8 word# nc we# v cc v ss clk k2 re s et# k1 v ccq v ccq v ss v ccq dq 3 a17 a16 a1 a15
june 7, 2006 am29bdd160g 9 pin configuration a ?1 = le as t si gn i f i c a nt a ddre ss bi t for the 16- bi t d a t a bus , a nd s elect s b etween the h i gh a nd low word . a ?1 is not us ed for the 3 2- bi t mode (word# = v ih ) . a0?a1 8 = 1 9 - bi t a ddre ss bus for 16 m b dev i ce . a 9 su pport s 12 v au to s elect i np u t s. dq0?dq 3 1= 3 2- bi t d a t a i np u t s /o u tp u t s /flo a t word# = s elect s 16- bi t or 3 2- bi t mode . when word# = v ih , d a t a is o u tp u t on dq 3 1?dq0 . when word# = v il , d a t a is o u tp u t on dq15?dq0 . ce# = ch i p en ab le inp u t . th is si gn a l is as ynchro- no us rel a t i ve to clk for the bu r s t mode . oe# = o u tp u t en ab le inp u t . th is si gn a l is as yn- chrono us rel a t i ve to clk for the bu r s t mode . we# = wr i te en ab le . th is si gn a l is as ynchrono us rel a t i ve to clk for the bu r s t mode . v ss = dev i ce gro u nd nc = p i n not connected i ntern a lly ry/by# = re a dy/b us y o u tp u t a nd open dr ai n . when ry/by# = v ih , the dev i ce is re a dy to a c- cept re a d oper a t i on s a nd comm a nd s. when ry/by# = v ol , the dev i ce is e i ther exec u t i ng a n em b edded a lgor i thm or the dev i ce is exec u t i ng a h a rdw a re re s et oper- a t i on . clk = clock inp u t th a t c a n b e t i ed to the s y s tem or m i croproce ss or clock a nd prov i de s the f u nd a ment a l t i m i ng a nd i ntern a l oper a t i ng fre qu ency . adv# = lo a d b u r s t addre ss i np u t . ind i c a te s th a t the v a l i d a ddre ss is pre s ent on the a ddre ss i np u t s. ind# = end of bu r s t i nd i c a tor for f i n i te bu r s t s only . ind is low when the l as t word i n the bu r s t s e qu ence is a t the d a t a o u tp u t s. wait# = prov i de s d a t a v a l i d feed ba ck only when the bu r s t length is s et to cont i n u o us. wp# = wr i te protect i np u t . when wp# = v ol , the two o u termo s t b oot b lock s ector i n the 75 % ba nk a re wr i te protected reg a rdle ss of other s ector protect i on conf i g u r a t i on s. acc = acceler a t i on i np u t . when t a ken to 12 v, progr a m a nd er as e oper a t i on s a re a cceler- a ted . when not us ed for a cceler a t i on, acc = v ss to v cc . v io (v ccq )= o u tp u t b u ffer power su pply (1 . 65 v to 2 . 75 v) v cc = ch i p power su pply (2 . 5 v to 2 . 75 v) re s et# = h a rdw a re re s et i np u t logic s ymbol s x16 mode x 3 2 mode 20 16 dq0?dq15 a-1 to a1 8 clk ry/by# ind/wait# ce# oe# we# re s et# adv# acc wp# v io (v ccq ) word# 1 9 3 2 dq0?dq 3 1 a0?a1 8 clk ry/by# ind/wait# ce# oe# we# re s et# adv# acc wp# v io (v ccq ) word#
10 am29bdd160g june 7, 2006 ordering information standard products amd standard products are available in several packages and o perating ranges. the order number (valid combination) is formed by a combination of the following: valid combinations valid combinations list configurations planned to be supported in vol- ume for this device. consult the lo cal amd sales office to confirm availability of specific valid combinations and to check on newly re- leased combinations. am29bdd160 g t 54 d pb e temperature range i = industrial (?40 c to +85 c) f = industrial (?40 c to +85 c) with pb-free package e = extended (?40 c to +125 c) k = extended (?40 c to +125 c) with pb-free package pack age type k = 80-pin plastic quad flat package (pqfp) pqr080 pb = 80-ball fortified ball grid array (fortified bga) 1.0 mm pitch, 13 x 11 mm package (laa080) clock rate a = 40 mhz c = 56 mhz d = 66 mhz speed option see product selector guide and valid combinations sector architecture t = top sector b = bottom sector process technology g = 0.17 m device number/description am29bdd160g 16 megabit (1 m x 16-bit/512 k x 32-bit) cmos 2.5 volt-only burst mode, dual boot, simultaneous read/write flash memory valid combinations for pfqp packages am29bdd160gt54d, am29bdd160gb54d ki, ke, kf, kk am29bdd160gt64c, am29bdd160gb64c am29bdd160gt65a, am29bdd160gb65a valid combinations for fortified bga packages order number package marking am29bdd160gt54d, am29bdd160gb54d pbi, pbe bd160gt54d, bd160gb54d i, e, f, k am29bdd160gt64c, am29bdd160gb64c bd160gt64c, bd160gb64c am29bdd160gt65a, am29bdd160gb65a bd160gt65a, bd160gb65a
june 7, 2006 am29bdd160g 11 device bu s operation s th is s ect i on de s cr ib e s the re qui rement s a nd us e of the dev i ce bus oper a t i on s , wh i ch a re i n i t ia ted thro u gh the i ntern a l comm a nd reg is ter . the comm a nd reg is ter i t s elf doe s not occ u py a ny a ddre ssab le memory loc a t i on . the reg is ter is compo s ed of l a tche s th a t s tore the com- m a nd s , a long w i th the a ddre ss a nd d a t a i nform a t i on needed to exec u te the comm a nd . the content s of the reg is ter s erve as i np u t s to the i ntern a l s t a te m a ch i ne . the s t a te m a ch i ne o u tp u t s d i ct a te the f u nct i on of the dev i ce . t ab le 1 l is t s the dev i ce bus oper a t i on s , the i n- p u t s a nd control level s they re qui re, a nd the re su lt i ng o u tp u t . the follow i ng subs ect i on s de s cr ib e e a ch of the s e oper a t i on s i n f u rther det ai l .
12 am29bdd160g june 7, 2006 legend: l = log i c low = v il , h = log i c h i gh = v ih , x = don?t c a re . notes: 1 . dq31?dq16 a re high z when word# = v il 2 . when word# = v il , dq31-dq16 a re flo a t i ng 3 . wp# control s the two o u termo s t s ector s of the top b oot b lock or the two o u termo s t s ector s of the b ottom b oot b lock . 4 . dq0 reflect s the s ector ppb (or s ector gro u p ppb) a nd dq1 reflect s the dyb 5 . addre ss e s a re a0 : a18 for the x32 mode a nd a?1 : a18 for x16 mode . table 1 . dev i ce bu s operat i on operat i on ce# oe# we# re s et# clk adv# addre ss e s (note 1) data (dq0?dq 3 1) a u to s elect m a n u f a ct u rer code l l h h x x a 9 = v id , a6 = l, a1 = l, a0 = l 0000001h (note 2) a u to s elect dev i ce code re a d cycle 1 l l h h x x a 9 = v id , a6 = l, a1 = l, a0 = h 000007eh (note 2) re a d cycle 2 l l h h x x a 9 = v id , a7?a0 = 0eh 000000 8 h re a d cycle 3 llh h xx a 9 = v id , a7?a0 = 0fh top boot block 0000000h bottom boot block 0000001h re a d l l h h x x a in d out wr i te l h l h x x a in d in s t a nd b y (ce#) h x x h x x x high z o u tp u t d isab le l h h h x x high z high z re s et x x x l x x x high z ppb protect i on s t a t us (note 4) l l h h x x s ector addre ss , a 9 = v id , a7 ? a0 = 02h 00000001h, (protected) a6 = h 00000000h ( u nprotect) a6 = l bur s t read operat i on s lo a d s t a rt i ng b u r s t addre ss lxh h a in x adv a nce b u r s t to next a ddre ss w i th a ppropr ia te d a t a pre s ented on the d a t a bus llh h h x b u r s t d a t a o u t te r m i n a te c u rrent b u r s t re a d cycle hxh h x x high z te r m i n a te c u rrent b u r s t re a d cycle w i th re s et# xxh l xx x high z te r m i n a te c u rrent b u r s t re a d cycle ; s t a rt new b u r s t re a d cycle lhh h a in x
june 7, 2006 am29bdd160g 13 ver s at i lei/o? (v io ) control the ver sa t i lei/o (v io ) control a llow s the ho s t s y s tem to s et the volt a ge level s th a t the dev i ce gener a te s a t i t s d a t a o u tp u t s a nd the volt a ge s toler a ted a t i t s d a t a i np u t s to the sa me volt a ge level th a t is ass erted on the v io p i n . the o u tp u t volt a ge gener a ted on the dev i ce is deter- m i ned bas ed on the v io (v ccq ) level . a v io of 1 . 65?1 .9 5 volt s is t a rgeted to prov i de for i/o toler a nce a t the 1 .8 volt level . a v cc a nd v io of 2 . 5?2 . 75 volt s m a ke s the dev i ce a p- pe a r as 2 . 5 volt-only . addre ss /control si gn a l s a re 3. 6 v toler a nt w i th the ex- cept i on of clk . word/double word conf ig urat i on the word# p i n control s whether the dev i ce d a t a i/o p i n s oper a te i n the word or do ub le word conf i g u r a t i on . if the word# p i n is s et a t v ih , the dev i ce is i n do ub le word conf i g u r a t i on, dq 3 1?dq0 a re a ct i ve a nd con- trolled b y ce# a nd oe# . if the word# p i n is s et a t v il , the dev i ce is i n word conf i g u r a t i on, a nd only d a t a i/o p i n s dq15?dq0 a re a ct i ve a nd controlled b y ce# a nd oe# . the d a t a i/o p i n s dq 3 1?dq16 a re tr i - s t a ted . requ i rement s for read i n g array data to r e a d a rr a y d a t a from the o u tp u t s , the s y s tem m us t dr i ve the ce# a nd oe# p i n s to v il . ce# is the power control a nd s elect s the dev i ce . oe# is the o u tp u t con- trol a nd g a te s a rr a y d a t a to the o u tp u t p i n s. we# s ho u ld rem ai n a t v ih . the i ntern a l s t a te m a ch i ne is s et for re a d i ng a rr a y d a t a u pon dev i ce power- u p, or a fter a h a rdw a re re s et . th is en su re s th a t no s p u r i o us a lter a t i on of the memory content occ u r s d u r i ng the power tr a n si t i on . no com- m a nd is nece ssa ry i n th is mode to o b t ai n a rr a y d a t a. s t a nd a rd m i croproce ss or re a d cycle s th a t ass ert v a l i d a ddre ss e s on the dev i ce a ddre ss i np u t s prod u ce v a l i d d a t a on the dev i ce d a t a o u tp u t s. the dev i ce rem ai n s en ab led for re a d a cce ss u nt i l the comm a nd reg is ter content s a re a ltered . addre ss a cce ss t i me (t acc ) is the del a y from s t ab le a d- dre ss e s to v a l i d o u tp u t d a t a. the ch i p en ab le a cce ss t i me (t ce ) is the del a y from s t ab le a ddre ss e s a nd s t a - b le ce# to v a l i d d a t a a t the o u tp u t p i n s. the o u tp u t en- ab le a cce ss t i me (t oe ) is the del a y from the f a ll i ng edge of oe# to v a l i d d a t a a t the o u tp u t p i n s ( assu m i ng the a ddre ss e s h a ve b een s t ab le for a t le as t t acc ?t oe t i me a nd ce# h as b een ass erted for a t le as t t ce ?t oe t i me) . s ee ?re a d i ng arr a y d a t a ? for more i nform a t i on . refer to the ac re a d oper a t i on s t ab le for t i m i ng s pec i f i c a - t i on s a nd to f i g u re 15 for the t i m i ng d ia gr a m . i cc1 i n the dc ch a r a cter is t i c s t ab le repre s ent s the a ct i ve c u r- rent s pec i f i c a t i on for re a d i ng a rr a y d a t a. si multaneou s read/wr i te operat i on s overv i ew and re s tr i ct i on s overv i ew si m u lt a neo us oper a t i on is a n a dv a nce s f u nct i on a l i ty prov i d i ng enh a nced s peed a nd flex ibi l i ty w i th m i n i m u m overhe a d . si m u lt a neo us oper a t i on doe s th is b y a llow- i ng a n oper a t i on to b e exec u ted (em b edded oper a t i on) i n a ba nk ( bus y ba nk), then go i ng to the other ba nk (non- bus y ba nk) a nd perform i ng de si red oper a t i on s. the bdd160? s si m u lt a neo us oper a t i on h as b een opt i - m i zed for a ppl i c a t i on s th a t co u ld mo s t b enef i t from th is c a p abi l i ty . the s e a ppl i c a t i on s s tore code i n the bi g ba nk, wh i le s tor i ng d a t a i n the s m a ll ba nk . the b e s t ex a mple of th is is when a s ector er as e oper a t i on ( as a n em b edded oper a t i on) i n the s m a ll ( bus y) ba nk, wh i le perform i ng a b u r s t/ s ynchrono us re a d oper a t i on i n the bi g (non- bus y) ba nk . re s tr i ct i on s the bdd160? s si m u lt a neo us oper a t i on is te s ted b y exec u t i ng a n em b edded oper a t i on i n the s m a ll ( bus y) ba nk wh i le perform i ng other oper a t i on s i n the bi g (non- bus y) ba nk . however, the oppo si te c as e is ne i - ther te s ted nor v a l i d . th a t is , i t is not te s ted b y exec u t- i ng a n em b edded oper a t i on i n the bi g ( bus y) ba nk wh i le perform i ng other oper a t i on s i n the s m a ll (non- bus y) ba nk . s ee t ab le 2 b a nk assi gnment for boot b a nk s ector dev i ce s. table 2 . bank a ssig nment for boot bank s ector dev i ce s al s o s ee t ab le 1 8 , ?allowed oper a t i on s d u r i ng er as e/progr a m sus pend,? on p a ge 38. al s o s ee t ab le 12, ? s ector addre ss e s for top boot s ector de- v i ce s ,? on p a ge 2 9 a nd s ee t ab le 1 3 , ? s ector ad- dre ss e s for bottom boot s ector dev i ce s ,? on p a ge 3 0 . si multaneou s read/wr i te operat i on s w i th zero latency the dev i ce is c a p ab le of re a d i ng d a t a from one ba nk of memory wh i le progr a mm i ng or er asi ng i n the other ba nk of memory . an er as e oper a t i on m a y a l s o b e sus - pended to re a d from or progr a m to a nother loc a t i on w i th i n the sa me ba nk (except the s ector b e i ng er as ed) . refer to the dc ch a r a cter is t i c s t ab le for top boot s ector dev i ce s bottom boot s ector dev i ce s b a nk 1 s m a ll b a nk b i g b a nk b a nk 2 b i g b a nk s m a ll b a nk
14 am29bdd160g june 7, 2006 re a d-wh i le-progr a m a nd re a d-wh i le-er as e c u rrent s pec i f i c a t i on s. si m u lt a neo us re a d/wr i te oper a t i on s a re v a l i d for b oth the m ai n fl as h memory a rr a y a nd the s ec si otp s ec- tor . si m u lt a neo us oper a t i on is d isab led d u r i ng the cfi a nd p ass word progr a m/ver i fy oper a t i on s. ppb pro- gr a m/er as e oper a t i on s a nd the p ass word unlock op- er a t i on perm i t re a d i ng d a t a from the l a rge (75 % ) ba nk wh i le re a d i ng the oper a t i on s t a t us of the s e comm a nd s from the s m a ll (25 % ) ba nk . table 3. top boot bank s elect table 4 . bottom boot bank s elect wr i t i n g command s /command s equence s to w r i te a comm a nd or comm a nd s e qu ence (wh i ch i n- cl u de s progr a mm i ng d a t a to the dev i ce a nd er asi ng s ector s of memory), the s y s tem m us t dr i ve we# a nd ce# to v il , a nd oe# to v ih . for progr a m oper a t i on s , i n the x 3 2-mode the dev i ce a ccept s progr a m d a t a i n 3 2- bi t word s a nd i n the x16 mode the dev i ce a ccept s progr a m d a t a i n 16- bi t word s. the dev i ce fe a t u re s a n unlock bypa ss mode to f a c i l i - t a te f as ter progr a mm i ng . once the dev i ce enter s the unlock byp ass mode, only two wr i te cycle s a re re- qui red to progr a m a word or b yte, i n s te a d of fo u r . the s ector er as e a nd progr a m sus pend comm a nd s ec- t i on h as det ai l s on progr a mm i ng d a t a to the dev i ce usi ng b oth s t a nd a rd a nd unlock byp ass comm a nd s e- qu ence s. an er as e oper a t i on c a n er as e one s ector, m u lt i ple s ec- tor s , or the ent i re dev i ce . t ab le s 12 a nd 1 3 i nd i c a te the a ddre ss s p a ce th a t e a ch s ector occ u p i e s. a ? s ec- tor a ddre ss ? con sis t s of the a ddre ss bi t s re qui red to u n iqu ely s elect a s ector . the ?comm a nd def i n i t i on s ? s ect i on h as det ai l s on er asi ng a s ector or the ent i re ch i p, or sus pend i ng/re su m i ng the er as e oper a t i on . after the s y s tem wr i te s the au to s elect comm a nd s e- qu ence, the dev i ce enter s the au to s elect mode . the s y s tem c a n then re a d au to s elect code s from the i nter- n a l reg is ter (wh i ch is s ep a r a te from the memory a rr a y) on dq7?dq0 . s t a nd a rd re a d cycle t i m i ng a ppl i e s i n th is mode . refer to the ?a u to s elect mode? s ect i on for more i nform a t i on . i cc2 i n the dc ch a r a cter is t i c s t ab le repre s ent s the a c- t i ve c u rrent s pec i f i c a t i on for er as e or progr a m mode s. the ac ch a r a cter is t i c s s ect i on cont ai n s t i m i ng s pec i f i - c a t i on t ab le s a nd t i m i ng d ia gr a m s for er as e or pro- gr a m oper a t i on s. accelerated pro g ram and era s e operat i on s the dev i ce offer s a cceler a ted progr a m/er as e oper a - t i on s thro u gh the acc p i n . when the s y s tem ass ert s v hh (12v) on the acc p i n, the dev i ce au tom a t i c a lly enter s the unlock byp ass mode . the s y s tem m a y then wr i te the two-cycle unlock byp ass progr a m com- m a nd s e qu ence to do a cceler a ted progr a mm i ng . the dev i ce us e s the h i gher volt a ge on the acc p i n to a c- celer a te the oper a t i on . a s ector th a t is b e i ng protected w i th the wp# p i n w i ll s t i ll b e protect d u r i ng a cceler a ted progr a m or er as e . note th a t the acc p i n m us t not b e a t v hh d u r i ng a ny oper a t i on other th a n a cceler a ted progr a mm i ng, or dev i ce d a m a ge m a y re su lt . auto s elect funct i on s if the s y s tem wr i te s the au to s elect comm a nd s e- qu ence, the dev i ce enter s the au to s elect mode . the s y s tem c a n then re a d au to s elect code s from the i nter- n a l reg is ter (wh i ch is s ep a r a te from the memory a rr a y) on dq7?dq0 . s t a nd a rd re a d cycle t i m i ng s a pply i n th is mode . refer to the a u to s elect mode a nd a u to s e- lect comm a nd s e qu ence s ect i on s for more i nform a - t i on . automat i c s leep mode (a s m) the au tom a t i c s leep mode m i n i m i ze s fl as h dev i ce en- ergy con su mpt i on . wh i le i n as ynchrono us mode, the dev i ce au tom a t i c a lly en ab le s th is mode when a d- dre ss e s rem ai n s t ab le for t acc + 60 n s. the au tom a t i c s leep mode is i ndependent of the ce#, we# a nd oe# control si gn a l s. s t a nd a rd a ddre ss a cce ss t i m i ng s pro- v i de new d a t a when a ddre ss e s a re ch a nged . wh i le i n s leep mode, o u tp u t d a t a is l a tched a nd a lw a y s a v ai l- ab le to the s y s tem . wh i le i n s ynchrono us mode, the dev i ce au tom a t i c a lly en ab le s th is mode when e i ther the f i r s t a ct i ve clk level is gre a ter th a n t acc or the clk r u n s s lower th a n 5 mhz . note th a t a new bu r s t oper a t i on is re qui red to prov i de new d a t a. i cc 8 i n the ?dc ch a r a cter is t i c s ? s ect i on of p a ge 5 3 rep- re s ent s the au tom a t i c s leep mode c u rrent s pec i f i c a - t i on . s tandby mode when the s y s tem is not re s pond i ng or wr i t i ng to the dev i ce, i t c a n pl a ce the dev i ce i n the s t a nd b y mode . in th is mode, c u rrent con su mpt i on is gre a tly red u ced, a nd the o u tp u t s a re pl a ced i n the h i gh i mped a nce s t a te, i ndependent of the oe# i np u t . the dev i ce enter s the cmo s s t a nd b y mode when the ce# a nd re s et# i np u t s a re b oth held a t vcc 0 . 2 v . the dev i ce re qui re s s t a nd a rd a cce ss t i me (t ce ) for re a d a cce ss , b efore i t is re a dy to re a d d a t a. bank a1 8 :a17 b a nk 1 00 b a nk 2 01, 1x bank a1 8 b a nk 1 0x, 10 b a nk 2 11
june 7, 2006 am29bdd160g 15 if the dev i ce is de s elected d u r i ng er asu re or progr a m- m i ng, the dev i ce dr a w s a ct i ve c u rrent u nt i l the oper a - t i on is completed . i cc5 i n the ?dc ch a r a cter is t i c s ? s ect i on on p a ge 5 3 repre s ent s the s t a nd b y c u rrent s pec i f i c a t i on . caut i on : enter i ng the s t a nd b y mode v ia the re s et# p i n a l s o re s et s the dev i ce to the re a d mode a nd flo a t s the d a t a i/o p i n s. f u rthermore, enter i ng i cc7 d u r i ng a progr a m or er as e oper a t i on w i ll le a ve erroneo us d a t a i n the a ddre ss loc a t i on s b e i ng oper a ted on a t the t i me of the re s et# p u l s e . the s e loc a t i on s re qui re u pd a t- i ng a fter the dev i ce re su me s s t a nd a rd oper a t i on s. refer to the ?re s et# : h a rdw a re re s et p i n? s ect i on for f u rther d is c ussi on of the re s et# p i n a nd i t s f u nc- t i on s. re s et#: hardware re s et p i n the re s et# p i n is a n a ct i ve low si gn a l th a t is us ed to re s et the dev i ce u nder a ny c i rc u m s t a nce s. a log i c ?0? on th is p i n force s the dev i ce o u t of a ny mode th a t is c u rrently exec u t i ng ba ck to the re s et s t a te . the re- s et# p i n m a y b e t i ed to the s y s tem re s et c i rc ui try . a s y s tem re s et wo u ld th us a l s o re s et the dev i ce . to a vo i d a potent ia l bus content i on d u r i ng a s y s tem re s et, the dev i ce is is ol a ted from the dq d a t a bus b y tr is t a t- i ng the d a t a o u tp u t p i n s for the d u r a t i on of the re s et p u l s e . all p i n s a re ?don?t c a re? d u r i ng the re s et oper a - t i on . if re s et# is ass erted d u r i ng a progr a m or er as e op- er a t i on, the ry/by# p i n rem ai n s low u nt i l the re s et op- er a t i on is i ntern a lly complete . th is a ct i on re qui re s b etween 1 s a nd 7 s for e i ther ch i p er as e or s ector er as e . the ry/by# p i n c a n b e us ed to determ i ne when the re s et oper a t i on is complete . otherw is e, a llow for the m a x i m u m re s et t i me of 11 s. if re s et# is ass erted when a progr a m or er as e oper a t i on is not exec u t i ng (ry/by# = ?1?), the re s et oper a t i on w i ll com- plete w i th i n 500 n s. si nce the am2 9 bdd160 is a si - m u lt a neo us oper a t i on dev i ce the us er m a y re a d a ba nk a fter 500 n s i f the ba nk w as i n the re a d/re s et mode a t the t i me re s et# w as ass erted . if one of the ba nk s w as i n the m i ddle of e i ther a progr a m or er as e oper a t i on when re s et# w as ass erted, the us er m us t w ai t 11 s b efore a cce ssi ng th a t ba nk . a ss ert i ng re s et# d u r i ng a progr a m or er as e oper a - t i on le a ve s erroneo us d a t a s tored i n the a ddre ss loc a - t i on s b e i ng oper a ted on a t the t i me of dev i ce re s et . the s e loc a t i on s need u pd a t i ng a fter the re s et oper a - t i on is complete . s ee f i g u re 1 9 for t i m i ng s pec i f i c a - t i on s. a ss ert i ng re s et# a ct i ve d u r i ng v cc a nd v io power- u p is re qui red to g ua r a ntee proper dev i ce i n i - t ia l i z a t i on u nt i l v cc a nd v io h a ve re a ched the i r s te a dy s t a te volt a ge s. output d is able mode s ee t ab le 1 dev i ce b us oper a t i on for oe# oper a t i on i n o u tp u t d isab le mode . auto s elect mode the au to s elect mode prov i de s m a n u f a ct u rer a nd de- v i ce i dent i f i c a t i on, a nd s ector protect i on ver i f i c a t i on, thro u gh i dent i f i er code s o u tp u t on dq7?dq0 . th is mode is pr i m a r i ly i ntended for progr a mm i ng e qui p- ment to au tom a t i c a lly m a tch a dev i ce to b e pro- gr a mmed w i th i t s corre s pond i ng progr a mm i ng a lgor i thm . however, the au to s elect code s c a n a l s o b e a cce ss ed i n- s y s tem thro u gh the comm a nd reg is ter . when usi ng progr a mm i ng e qui pment, the au to s elect mode re qui re s v id on a ddre ss p i n a 9. addre ss p i n s a6, a1, a nd a0 m us t b e as s hown i n t ab le 12 (top b oot dev i ce s ) or t ab le 1 3 ( b ottom b oot dev i ce s ) . in a d- d i t i on, when ver i fy i ng s ector protect i on, the s ector a d- dre ss m us t a ppe a r on the a ppropr ia te h i ghe s t order a ddre ss bi t s ( s ee t ab le s 11 a nd 12) . s ee t ab le 5 s how s the rem ai n i ng a ddre ss bi t s th a t a re don?t c a re . when a ll nece ssa ry bi t s h a ve b een s et as re qui red, the progr a mm i ng e qui pment m a y then re a d the corre- s pond i ng i dent i f i er code on dq7?dq0 . to a cce ss the au to s elect code s i n- s y s tem, the ho s t s y s tem c a n issu e the au to s elect comm a nd v ia the comm a nd . th is method doe s not re qui re v id . s ee ?comm a nd def i n i t i on s ? for det ai l s on usi ng the au to s e- lect mode .
16 am29bdd160g june 7, 2006 table 5 . am29bdd160 auto s elect code s (h ig h volta g e method) l = log i c low = v il , h = log i c h i gh = v ih , sa = sector addre ss , x = don?t c a re . note: the au to s elect code s m a y a l s o b e a cce ss ed i n- s y s tem v ia comm a nd s e qu ence s. see t ab le s 18 a nd 20 . a s ynchronou s read operat i on (non-bur s t) the dev i ce h as two control f u nct i on s wh i ch m us t b e sa t is f i ed i n order to o b t ai n d a t a a t the o u tp u t s. ce# is the power control a nd s ho u ld b e us ed for dev i ce s elec- t i on . oe# is the o u tp u t control a nd s ho u ld b e us ed to g a te d a t a to the o u tp u t p i n s i f the dev i ce is s elected . the dev i ce is power- u p i n a n as ynchrono us re a d mode . in the as ynchrono us mode the dev i ce h as two control f u nct i on s wh i ch m us t b e sa t is f i ed i n order to o b t ai n d a t a a t the o u tp u t s. ce# is the power control a nd s ho u ld b e us ed for dev i ce s elect i on . oe# is the o u tp u t control a nd s ho u ld b e us ed to g a te d a t a to the o u tp u t p i n s i f the dev i ce is s elected . addre ss a cce ss t i me (t acc ) is e qua l to the del a y from s t ab le a ddre ss e s to v a l i d o u tp u t d a t a. the ch i p en ab le a cce ss t i me (t ce ) is the del a y from the s t ab le a d- dre ss e s a nd s t ab le ce# to v a l i d d a t a a t the o u tp u t p i n s. the o u tp u t en ab le a cce ss t i me is the del a y from the f a ll i ng edge of oe# to v a l i d d a t a a t the o u tp u t p i n s ( assu m i ng the a ddre ss e s h a ve b een s t ab le for a t le as t t acc ?t oe t i me) . note: oper a t i on is s hown for the 32- bi t d a t a bus. for the 16- bi t d a t a bus , a-1 is re qui red . f ig ure 1 . a s ynchronou s read operat i on de s cr i pt i on ce# oe# we# a1 8 to a11 a10 a9 a 8 a7 a6 a5 to a4 a 3 a2 a1 a0 dq7 to dq0 m a n u f a ct u rer id : amd llhxxv id xxlxxxll 0001h a u to s elect dev i ce code re a d cycle 1 l l h x x v id xllxlllh 007eh re a d cycle 2 l l h x x v id xlllhhhl 000 8 h re a d cycle 3 llhxxv id x l l lhhhh 0000h (top b oot b lock) 0001h ( b ottom b oot b lock) ppb protect i on s t a t us llh s ax v id xlllllhl 0000h ( u nprotected) 0001h (protected) d0 d1 d2 d 3 d 3 ce# clk adv# a0 - a1 8 dq0 - dq 3 1 oe# we# ind/wait# v ih flo a t v oh addre ss 0 addre ss 1 addre ss 2 addre ss 3 flo a t
june 7, 2006 am29bdd160g 17 s ynchronou s (bur s t) read operat i on the am2 9 bdd160 is c a p ab le of perform i ng bu r s t re a d oper a t i on s to i mprove tot a l s y s tem d a t a thro u ghp u t . the dev i ce is a v ai l ab le i n three bu r s t mode s of oper a - t i on : l i ne a r a nd bu r s t mode . 2, 4 a nd 8 do ub le word (x 3 2) a nd 4 a nd 8 word (x16) a cce ss e s a re conf i g- u r ab le as e i ther s e qu ent ia l bu r s t a cce ss e s. 16 a nd 3 2 word (x16) a cce ss e s a re only conf i g u r ab le as l i ne a r bu r s t a cce ss e s. add i t i on a l opt i on s for a ll bu r s t mode s i ncl u de i n i t ia l a cce ss del a y conf i g u r a t i on s (2?16 clk s ) dev i ce conf i g u r a t i on for bu r s t mode oper a t i on is a ccompl is hed b y wr i t i ng the conf i g u r a t i on reg is ter w i th the de si red bu r s t conf i g u r a t i on i nform a t i on . once the conf i g u r a t i on reg is ter is wr i tten to en ab le bu r s t mode oper a t i on, a ll subs e qu ent re a d s from the a rr a y a re ret u rned usi ng the bu r s t mode protocol s. l i ke the m ai n memory a cce ss , the s ec si s ector memory is a c- ce ss ed w i th the sa me bu r s t or as ynchrono us t i m i ng as def i ned i n the conf i g u r a t i on reg is ter . however, the us er m us t recogn i ze th a t cont i n u o us bu r s t oper a t i on s p as t the 256 b yte s ec si b o u nd a ry ret u rn s i nv a l i d d a t a. b u r s t re a d oper a t i on s occ u r only to the m ai n fl as h memory a rr a y s. the conf i g u r a t i on reg is ter a nd pro- tect i on bi t s a re tre a ted as si ngle cycle re a d s , even when bu r s t mode is en ab led . re a d oper a t i on s to the s e loc a t i on s re su lt s i n the d a t a rem ai n i ng v a l i d wh i le oe# is a t v il , reg a rdle ss of the n u m b er of clk cycle s a ppl i ed to the dev i ce . l i near bur s t read operat i on s l i ne a r bu r s t re a d mode re a d s e i ther 4, 8 , 16, or 3 2 word s (1 word = 16 bi t s ), depend i ng u pon the conf i g u - r a t i on reg is ter opt i on . if the dev i ce is conf i g u red w i th a 3 2 bi t i nterf a ce (word# = v ih ), the bu r s t a cce ss is compr is ed of 4 clocked re a d s for 8 word s a nd 16 clocked re a d s for 3 2 word s ( s ee t ab le 6 for a ll v a l i d bu r s t o u tp u t s e qu ence s ) . the n u m b er of clocked re a d s is do ub led when the dev i ce is conf i g u red i n the 16- bi t d a t a bus mode (word# = v il ) . the ind/wait# p i n tr a n si t i on s a ct i ve (v il ) d u r i ng the l as t tr a n s fer of d a t a d u r i ng a l i ne a r bu r s t re a d b efore a wr a p a ro u nd, i nd i c a t i ng th a t the s y s tem s ho u ld i n i t ia te a nother adv# to s t a rt the next bu r s t a cce ss. if the s y s tem con- t i n u e s to clock the dev i ce, the next a cce ss wr a p s a ro u nd to the s t a rt i ng a ddre ss of the prev i o us bu r s t a cce ss. the ind/wait# si gn a l rem ai n s i n a ct i ve (flo a t- i ng) when not a ct i ve . s ee t ab le 6 for a complete 3 2 a nd 16 bi t d a t a bus i nterf a ce order . 16 a nd 3 2 word opt i on s a re re s tr i cted to s e qu ent ia l bu r s t a cce ss e s , only . table 6 . 16-b i t and 3 2-b i t l i near and bur s tdataorder data tran s fer s equence (independent of the word# p i n) output data s equence (in i t i al acce ss addre ss ) (x16) two l i ne a r d a t a tr a n s fer s , (x 3 2 only) 0-1 (a0 = 0) 1-0 (a0 = 1) fo u r l i ne a r d a t a tr a n s fer s 0-1-2- 3 (a0 : a-1/a1-a0 = 00) 1-2- 3 -0 (a0 : a-1/a1-a0 = 01) 2- 3 -0-1 (a : a-1/a1-a0 = 10) 3 -0-1-2 (a0 : a-1/a1-a0 = 11) e i ght l i ne a r d a t a tr a n s fer s 0-1-2- 3 -4-5-6-7 (a1 : a-1a2-a0 = 000) 1-2- 3 -4-5-6-7-0 (a1 : a-1/a2-a0 = 001) 2- 3 -4-5-6-7-0-1 (a1 : a-1/a2-a0 = 010) 3 -4-5-6-7-0-1-2 (a1 : a-1/a2-a0 = 011) 4-5-6-7-0-1-2- 3 (a1 : a-1/a2-a0 = 100) 5-6-7-0-1-2- 3 -4 (a1 : a-1/a2-a0 = 101) 6-7-0-1-2- 3 -4-5 (a1 : a-1/a2-a0 = 110) 7-0-1-2- 3 -4-5-6 (a1 : a-1/a2-a0 = 111)
18 am29bdd160g june 7, 2006 ce# control i n l i near mode the ce# (ch i p en ab le) p i n en ab le s the am2 9 bdd160 d u r i ng re a d mode oper a t i on s. ce# m us t meet the re- qui red bu r s t re a d s et u p t i me s for bu r s t cycle i n i t ia t i on . if ce# is t a ken to v ih a t a ny t i me d u r i ng the bu r s t l i n- e a r or bu r s t cycle, the dev i ce i mmed ia tely ex i t s the bu r s t s e qu ence a nd flo a t s the dq bus a nd ind/wait# si gn a l . re s t a rt i ng a bu r s t cycle is a ccompl is hed b y t a k i ng ce# a nd adv# to v il . adv# control in l i near mode the adv# (addre ss v a l i d) p i n is us ed to i n i t ia te a l i n- e a r bu r s t cycle a t the clock edge when ce# a nd adv# a re a t v il a nd the dev i ce is conf i g u red for e i ther l i ne a r bu r s t mode oper a t i on . a bu r s t a cce ss is i n i t ia ted a nd the a ddre ss is l a tched on the f i r s t r isi ng clk edge when adv# is a ct i ve or u pon a r isi ng adv# edge, wh i chever occ u r s f i r s t . if the adv# si gn a l is t a ken to v il pr i or to the end of a l i ne a r bu r s t s e qu ence, the pre- v i o us a ddre ss is d is c a rded a nd subs e qu ent bu r s t tr a n s fer s a re i nv a l i d u nt i l adv# tr a n si t i on s to v ih b e- fore a clock edge, wh i ch i n i t ia te s a new bu r s t s e- qu ence . re s et# control i n l i near mode the re s et# p i n i mmed ia tely h a lt s the l i ne a r bu r s t a c- ce ss when t a ken to v il . the dq d a t a bus a nd ind/wait# si gn a l flo a t . add i t i on a lly, the conf i g u r a t i on reg is ter content s a re re s et ba ck to the def au lt cond i - t i on where the dev i ce is pl a ced i n as ynchrono us a c- ce ss mode . oe# control i n l i near mode the oe# (o u tp u t en ab le) p i n is us ed to en ab le the l i n- e a r bu r s t d a t a on the dq d a t a bus a nd the ind/wait# p i n . de- ass ert i ng the oe# p i n to v ih d u r i ng a bu r s t op- er a t i on flo a t s the d a t a bus a nd the ind/wait# p i n . however, the dev i ce w i ll cont i n u e to oper a te i ntern a lly as i f the bu r s t s e qu ence cont i n u e s u nt i l the l i ne a r bu r s t is complete . the oe# p i n doe s not h a lt the bu r s t s e- qu ence, th is is a ccompl is hed b y e i ther t a k i ng ce# to v ih or re- issui ng a new adv# p u l s e . the dq bus a nd ind/wait# si gn a l rem ai n i n the flo a t s t a te u nt i l oe# is t a ken to v il . ind/wait# operat i on i n l i near mode the ind/wait#, or end of b u r s t ind i c a tor si gn a l (when i n l i ne a r mode s ), i nform s the s y s tem th a t the l as t a ddre ss of a bu r s t s e qu ence is on the dq d a t a bus. for ex a mple, i f a 4-word l i ne a r bu r s t a cce ss is si xteen l i ne a r d a t a tr a n s fer s (x16 only) 0-1-2- 3 -4-5-6-7- 8 - 9 -a-b-c-d-e-f (a2 : a-1/ a 3 -a0 = 0000) 1-2- 3 -4-5-6-7- 8 - 9 -a-b-c-d-e-f-0 (a2 : a-1/ a 3 -a0 = 0001) 2- 3 -4-5-6-7- 8 - 9 -a-b-c-d-e-f-0-1 (a2 : a-1/ a 3 -a0 = 0010) 3 -4-5-6-7- 8 - 9 -a-b-c-d-e-f-0-1-2 (a2 : a-1/ a 3 -a0 = 0011) 4-5-6-7- 8 - 9 -a-b-c-d-e-f-0-1-2- 3 (a : a-1/ a 3 -a0 = 0100) 5-6-7- 8 - 9 -a-b-c-d-e-f-0-1-2- 3 -4 (a2 : a-1/ a 3 -a0 = 0101) 6-7- 8 - 9 -a-b-c-d-e-f-0-1-2- 3 -4-5 (a2 : a-1/ a 3 -a0 = 0110) 7- 8 - 9 -a-b-c-d-e-f-0-1-2- 3 -4-5-6 (a2 : a-1/ a 3 -a0 = 0111) 8 - 9 -a-b-c-d-e-f-0-1-2- 3 -4-5-6-7 (a2 : a-1/ a 3 -a0 = 1000) 9 -a-b-c-d-e-f-0-1-2- 3 -4-5-6-7- 8 (a2 : a-1/ a 3 -a0 = 1001) a-b-c-d-e-f-0-1-2- 3 -4-5-6-7- 8 - 9 (a2 : a-1/ a 3 -a0 = 1010) b-c-d-e-f-0-1-2- 3 -4-5-6-7- 8 - 9 -a (a2 : a-1/ a 3 -a0 = 1011) c-d-e-f-0-1-2- 3 -4-5-6-7- 8 - 9 -a-b (a2 : a-1/ a 3 -a0 = 1100) d-e-f-0-1-2- 3 -4-5-6-7- 8 - 9 -a-b-c (a2 : a-1/ a 3 -a0 = 1101) e-f-0-1-2- 3 -4-5-6-7- 8 - 9 -a-b-c-d (a2 : a-1/ a 3 -a0 = 1110) f-0-1-2- 3 -4-5-6-7- 8 - 9 -a-b-c-d-e (a2 : a-1/ a 3 -a0 = 1111) th i rty-two l i ne a r d a t a tr a n s fer s 0-1-2- 3 -4-5-6-7- 8 - 9 -a-b-c-d-e-f-g-h-i-j-k-l-m-n-o-p-q-r- s -t-u-v (a 3: a-1 = 00000) 1-2- 3 -4-5-6-7- 8 - 9 -a-b-c-d-e-f-g-h-i-j-k-l-m-n-o-p-q-r- s -t-u-v-0 (a 3: a-1 = 00001) : u-v-0-1-2- 3 -4-5-6-7- 8 - 9 -a-b-c-d-e-f-g-h-i-j-k-l-m-n-o-p-q-r- s -t (a 3: a-1 = 11110) v-0-1-2- 3 -4-5-6-7- 8 - 9 -a-b-c-d-e-f-g-h-i-j-k-l-m-n-o-p-q-r- s -t-u (a 3: a-1 = 11111) table 6 . 16-b i t and 3 2-b i t l i near and bur s t data order (cont i nued) data tran s fer s equence (independent of the word# p i n) output data s equence (in i t i al acce ss addre ss ) (x16)
june 7, 2006 am29bdd160g 19 en ab led usi ng a 16- bi t dq bus (word# = v il ), the ind/wait# si gn a l tr a n si t i on s a ct i ve on the fo u rth a c- ce ss. if the sa me s cen a r i o is us ed, bu t i n s te a d the 3 2- bi t dq bus is en ab led, the ind/wait# si gn a l tr a n si - t i on s a ct i ve on the s econd a cce ss. the ind/wait# si gn a l h as the sa me del a y a nd s et u p t i m i ng as the dq p i n s. al s o, the ind/wait# si gn a l is controlled b y the oe# si gn a l . if oe# is a t v ih , the ind/wait# si gn a l flo a t s a nd is not dr i ven . if oe# is a t v il , the ind/wait# si gn a l is dr i ven a t v ih u nt i l i t tr a n si t i on s to v il i nd i c a t i ng the end of bu r s t s e qu ence . the ind/wait# si gn a l t i m- i ng a nd d u r a t i on is ( s ee ?conf i g u r a t i on reg is ter? for more i nform a t i on) . the follow i ng t ab le l is t s the v a l i d com bi n a t i on s of the conf i g u r a t i on reg is ter bi t s th a t i mp a ct the ind/wait# t i m i ng .
20 am29bdd160g june 7, 2006 table 7 . val i d conf ig urat i on re gis ter b i t def i n i t i on for ind/wait# note: oper a t i on is s hown for the 32- bi t d a t a bus. for a 16- bi t d a t a bus , a-1 is re qui red . f i g u re s hown w i th 3-clk i n i t ia l a cce ss del a y conf i g u r a t i on, l i ne a r a ddre ss , 4-do ub leword bu r s t, o u tp u t on r isi ng clk edge, d a t a hold for 1-clk, ind/wait# ass erted on the l as t tr a n s fer b efore wr a p- a ro u nd . f ig ure 2 . end of bur s t ind i cator (ind/wait#) t i m i n g for l i near 8 -word bur s t operat i on doc wc cc def i n i t i on 0 0 1 ind/wait# = v il for 1-clk cycle, act i ve on l as t tr a n s fer, dr i ven on r isi ng clk edge 0 1 1 ind/wait# = v il for 1-clk cycle, act i ve on s econd to l as t tr a n s fer, dr i ven on r isi ng clk edge ce# clk adv# a0 - a1 8 oe# addre ss 1 addre ss 2 inv a l i dd1d2d 3 d0 addre ss 1 l a tched 3 clock del a y ind/wait#
june 7, 2006 am29bdd160g 21 bur s t acce ss t i m i n g control in a dd i t i on to the ind/wait# si gn a l control, bu r s t con- trol s ex is t i n the control reg is ter for i n i t ia l a cce ss de- l a y, del i very of d a t a on the clk edge, a nd the length of t i me d a t a is held . in i t i al bur s t acce ss delay control the am2 9 bdd160 cont ai n s opt i on s for i n i t ia l a cce ss del a y of a bu r s t a cce ss. the i n i t ia l a cce ss del a y h as no effect on as ynchrono us re a d oper a t i on s. b u r s t in i t ia l acce ss del a y is def i ned as the n u m b er of clock cycle s th a t m us t el a p s e from the f i r s t v a l i d clock edge a fter adv# ass ert i on (or the r isi ng edge of adv#) u nt i l the f i r s t v a l i d clk edge when the d a t a is v a l i d . the bu r s t a cce ss is i n i t ia ted a nd the a ddre ss is l a tched on the f i r s t r isi ng clk edge when adv# is a c- t i ve or u pon a r isi ng adv# edge, wh i chever come s f i r s t . ( s ee t ab le 8 de s cr ib e s the i n i t ia l a cce ss del a y conf i g u r a t i on s. ) if the clock conf i g u r a t i on bi t i n the control reg is ter is s et to f a ll i ng edge (cr6 = 0), the def i n i t i on rem ai n s the sa me for the i n i t ia l del a y s ett i ng w i th the except i on th a t d a t a is v a l i d a fter the f a ll i ng edge . table 8. bur s t in i t i al acce ss delay f ig ure 3. in i t i al bur s t delay control notes: 1 . b u r s t a cce ss s t a rt s w i th a r isi ng clk edge a nd when adv# is a ct i ve . 2 . conf i g u r a t i on s reg is ter 6 is s et to 1 (cr6 = 1) . b u r s t s t a rt s a nd d a t a o u tp u t s on the r isi ng clk edge . 3 . cr [13-10] = 1 or three clock cycle s 4 . cr [13-10] = 2 or fo u r clock cycle s 5 . cr [13-10] = 3 or f i ve clock cycle s cr1 3 cr12 cr11 cr10 in i t i al bur s t acce ss (clk cycle s ) 54d, 64c, 65a 0000 2 0001 3 0010 4 0011 5 0100 6 0101 7 0 1 1 0 8 0111 9 clk adv# a1 8 - a0 dq 3 1 - dq0 3 dq 3 1 - dq0 4 dq 3 1 - dq0 5 v a l i d addre ss three clk del a y 2nd clk 3 rd clk 4th clk 5th clk 1 s t clk fo u r clk del a y addre ss 1 l a tched f i ve clk del a y d0 d1 d2 d 3 d0 d1 d2 d0 d1 d2 d 3 d4
22 am29bdd160g june 7, 2006 burst clk edge data delivery the am2 9 bdd160 is c a p ab le of del i ver i ng d a t a on e i - ther the r isi ng or f a ll i ng edge of clk . to d e l i ver d a t a on the r isi ng edge of clk, bi t 6 i n the control reg is ter (cr6) is s et to 1 . to d e l i ver d a t a on the f a ll i ng edge of clk, bi t 6 i n the control reg is ter is cle a red to 0 . the def au lt conf i g u r a t i on is s et to the r isi ng edge . burst data hold control the dev i ce is c a p ab le of hold i ng d a t a for one clk s. the def au lt conf i g u r a t i on is to hold d a t a for one clk a nd is the only v a l i d s t a te . asserting reset# during a burst access if re s et# is ass erted low d u r i ng a bu r s t a cce ss , the bu r s t a cce ss is i mmed ia tely term i n a ted a nd the dev i ce def au lt s ba ck to as ynchrono us re a d mode . refer to re s et# : h a rdw a re re s et p i n for more i nform a t i on on the re s et# f u nct i on . conf ig urat i on re gis ter the am2 9 bdd160 cont ai n s a conf i g u r a t i on reg is ter for conf i g u r i ng re a d a cce ss e s. the conf i g u r a t i on reg- is ter is a cce ss ed b y the conf i g u r a t i on reg is ter re a d a nd the conf i g u r a t i on reg is ter wr i te comm a nd s. the conf i g u r a t i on reg is ter doe s not occ u py a ny a ddre ss - ab le memory loc a t i on, bu t r a ther, is a cce ss ed b y the conf i g u r a t i on reg is ter comm a nd s. the conf i g u r a t i on reg is ter is re a d ab le a ny t i me, however, wr i t i ng the conf i g u r a t i on reg is ter is re s tr i cted to t i me s when the em b edded algor i thm? is not a ct i ve . if the us er a t- tempt s to wr i te the conf i g u r a t i on reg is ter wh i le the em b edded algor i thm? is a ct i ve, the wr i te oper a t i on is i gnored a nd the content s of the conf i g u r a t i on reg is ter rem ai n u nch a nged . the conf i g u r a t i on reg is ter is a 16 bi t d a t a f i eld wh i ch is a cce ss ed b y dq15?dq0 . d a t a on dq 3 1?dq16 is i gnored d u r i ng a wr i te oper a t i on when word# = v il . d u r i ng a re a d oper a t i on, dq 3 1?dq16 ret u rn s a ll ze- roe s. t ab le 9 s how s the conf i g u r a t i on reg is ter . al s o, conf i g u r a t i on reg is ter re a d s oper a te the sa me as a u - to s elect comm a nd re a d s. when the comm a nd is is - su ed, the ba nk a ddre ss is l a tched a long w i th the comm a nd . re a d s oper a t i on s to the ba nk th a t w as s pec i f i ed d u r i ng the conf i g u r a t i on reg is ter re a d com- m a nd ret u rn conf i g u r a t i on reg is ter content s. re a d oper a t i on s to the other ba nk ret u rn fl as h memory d a t a. e i ther ba nk a ddre ss is perm i tted when wr i t i ng the conf i g u r a t i on reg is ter re a d comm a nd . table 9 . conf ig urat i on re gis ter def i n i t i on s cr15 cr14 cr1 3 cr12 cr11 cr10 cr 9 cr 8 rm re s erved iad 3 iad2 iad1 iad0 doc wc cr7 cr6 cr5 cr4 cr 3 cr2 cr1 cr0 b s cc re s erved re s erved re s erved bl2 bl1 bl0 conf ig urat i on re gis ter cr15 = read mode (rm) 0 = s ynchrono us b u r s t re a d s en ab led 1 = a s ynchrono us re a d s en ab led (def au lt) cr14 = re s erved for future enhancement s the s e bi t s a re re s erved for f u t u re us e . s et the s e bi t s to ?0? .
june 7, 2006 am29bdd160g 23 cr1 3 ?cr10 = in i t i al bur s t acce ss delay conf ig urat i on (iad 3 -iad0) speed opt i on s 54d, 64c, 65a : 0000 = 2 clk cycle i n i t ia l bu r s t a cce ss del a y 0001 = 3 clk cycle i n i t ia l bu r s t a cce ss del a y 0010 = 4 clk cycle i n i t ia l bu r s t a cce ss del a y 0011 = 5 clk cycle i n i t ia l bu r s t a cce ss del a y 0100 = 6 clk cycle i n i t ia l bu r s t a cce ss del a y 0101 = 7 clk cycle i n i t ia l bu r s t a cce ss del a y 0110 = 8 clk cycle i n i t ia l bu r s t a cce ss del a y 0111 = 9 clk cycle i n i t ia l bu r s t a cce ss del a y?def au lt cr9 = data output conf ig urat i on (doc) 0 = hold d a t a for 1-clk cycle?def au lt 1 = re s erved cr 8 = ind/wait# conf ig urat i on (wc) 0 = ind/wait# a ss erted d u r i ng del a y?def au lt 1 = ind/wait# a ss erted one d a t a cycle before del a y cr7 = bur s t s equence (b s ) 0 = re s erved 1 = l i ne a r b u r s t order?def au lt cr6 = clock conf ig urat i on (cc) 0 = re s erved 1 = b u r s t s t a rt s a nd d a t a o u tp u t on r isi ng clock edge?def au lt cr5?cr 3 = re s erved for future enhancement s (r) the s e bi t s a re re s erved for f u t u re us e . s et the s e bi t s to ?0 . ? cr2?cr0 = bur s t len g th (bl2?bl0) 000 = re s erved, bu r s t a cce ss e s d isab led ( as ynchrono us re a d s only) 001 = 64 bi t ( 8 - b yte) b u r s t d a t a tr a n s fer - x16 a nd x 3 2 l i ne a r 010 = 12 8 bi t (16- b yte) b u r s t d a t a tr a n s fer - x16 a nd x 3 2 l i ne a r 011 = 256 bi t ( 3 2- b yte) b u r s t d a t a tr a n s fer - x16 l i ne a r only a nd x 3 2 l i ne a r 100 = 512 bi t (64- b yte) b u r s t d a t a tr a n s fer - x16 l i ne a r only - def au lt 101 = re s erved, bu r s t a cce ss e s d isab led ( as ynchrono us re a d s only) 110 = re s erved, bu r s t a cce ss e s d isab led ( as ynchrono us re a d s only) 111 = re s erved table 9 . conf ig urat i on re gis ter def i n i t i on s (cont i nued)
24 am29bdd160g june 7, 2006 in i t i al acce ss delay conf ig urat i on the fre qu ency conf i g u r a t i on i nform s the dev i ce of the n u m b er of clock s th a t m us t el a p s e a fter adv# is dr i ven a ct i ve b efore d a t a w i ll b e a v ai l ab le . th is v a l u e is determ i ned b y the i np u t clock fre qu ency . s ector protection the am2 9 bdd160 fe a t u re s s ever a l level s of s ector protect i on, wh i ch c a n d isab le b oth the progr a m a nd er as e oper a t i on s i n cert ai n s ector s or s ector gro u p s sector and sector groups the d is t i nct i on b etween s ector s a nd s ector gro u p s is f u nd a ment a l to s ector protect i on . s ector a re i nd i v i d ua l s ector s th a t c a n b e i nd i v i d ua lly s ector protected/ u n- protected . the s e a re the o u termo s t 4 kword b oot s ec- tor s , th a t is , s a0 to s a7 a nd s a 38 to s a45 . s ee t ab le s 11 a nd 12 . s ector gro u p s a re a collect i on of three or fo u r a d ja cent 3 2 kword s ector s. for ex a mple, s ector gro u p s g 8 is compr is ed of s ector s a 8 to s a10 . when a ny s ector i n a s ector gro u p is protected/ u nprotected, every s ector i n th a t gro u p is protect i on/ u nprotected . s ee t ab le s 11 a nd 12 . persistent sector protection a comm a nd s ector protect i on method th a t repl a ce s the old 12 v controlled protect i on method . password sector protection a h i ghly s oph is t i c a ted protect i on method th a t re qui re s a p ass word b efore ch a nge s to cert ai n s ector s or s ec- tor gro u p s a re perm i tted wp# hardware protection a wr i te protect p i n th a t c a n prevent progr a m or er as e to the two o u termo s t 8 k b yte s s ector s i n the 75 % ba nk all p a rt s def au lt to oper a te i n the per sis tent s ector protect i on mode . the c us tomer m us t then choo s e i f the per sis tent or p ass word protect i on method is mo s t de si r ab le . there a re two one-t i me progr a mm ab le non-vol a t i le bi t s th a t def i ne wh i ch s ector protect i on method w i ll b e us ed . if the c us tomer dec i de s to con- t i n u e usi ng the per sis tent s ector protect i on method, they m us t s et the per sis tent s ector protect i on mode lock i n g b i t . th is w i ll perm a nently s et the p a rt to oper a te only usi ng per sis tent s ector protect i on . if the c us tomer dec i de s to us e the p ass word method, they m us t s et the pa ss word mode lock i n g b i t . th is w i ll perm a nently s et the p a rt to oper a te only usi ng p ass word s ector protect i on . it is i mport a nt to remem b er th a t s ett i ng e i ther the per- sis tent s ector protect i on mode lock i n g b i t or the pa ss word mode lock i n g b i t perm a nently s elect s the protect i on mode . it is not po ssib le to s w i tch b e- tween the two method s once a lock i ng bi t h as b een s et . it is i mportant that one mode is expl i c i tly s e- lected when the dev i ce is f i r s t pro g rammed, rather than rely i n g on the default mode alone . th is is s o th a t i t is not po ssib le for a s y s tem progr a m or v i r us to l a ter s et the p ass word mode lock i ng b i t, wh i ch wo u ld c aus e a n u nexpected s h i ft from the def au lt per sis tent s ector protect i on mode i nto the p ass word protect i on mode . the wp# h a rdw a re protect i on fe a t u re is a lw a y s a v ai l- ab le, i ndependent of the s oftw a re m a n a ged protect i on method cho s en . per sis tent s ector protect i on the per sis tent s ector protect i on method repl a ce s the old 12 v controlled protect i on method wh i le a t the sa me t i me enh a nc i ng flex ibi l i ty b y prov i d i ng three d i f- ferent s ector protect i on s t a te s: per sis tently locked ?a s ector is protected a nd c a nnot b e ch a nged . dynam i cally locked ?the s ector is protected a nd c a n b e ch a nged b y a si mple comm a nd unlocked ?the s ector is u nprotected a nd c a n b e ch a nged b y a si mple comm a nd table 10 . conf ig urat i on re gis ter after dev i ce re s et cr15 cr14 cr1 3 cr12 cr11 cr10 cr 9 cr 8 rm re s erve iad 3 iad2 iad1 iad0 doc wc 10011100 cr7 cr6 cr5 cr4 cr 3 cr2 cr1 cr0 b s cc re s erve re s erve re s erve bl2 bl1 bl0 11000100
june 7, 2006 am29bdd160g 25 in order to a ch i eve the s e s t a te s , three type s of ? bi t s ? a re go i ng to b e us ed : per sis tent protect i on b i t (ppb) a si ngle per sis tent (non-vol a t i le) protect i on b i t is as - si gned to a m a x i m u m of fo u r s ector s ( s ee the s ector a ddre ss t ab le s for s pec i f i c s ector protect i on gro u p- i ng s ) . all 8 k b yte b oot- b lock s ector s h a ve i nd i v i d ua l s ector per sis tent protect i on b i t s (ppb s ) for gre a ter flex ibi l i ty . e a ch ppb is i nd i v i d ua lly mod i f iab le thro u gh the ppb wr i te command . note : if a ppb re qui re s er asu re, a ll of the s ector ppb s m us t f i r s t b e preprogr a mmed pr i or to ppb er asi ng . all ppb s er as e i n p a r a llel, u nl i ke progr a mm i ng where i n- d i v i d ua l ppb s a re progr a mm ab le . it is the re s pon sibi l- i ty of the us er to perform the preprogr a mm i ng oper a t i on . otherw is e, a n a lre a dy er as ed s ector ppb s h as the potent ia l of b e i ng over-er as ed . there is no h a rdw a re mech a n is m to prevent s ector ppb s over-er asu re . per sis tent protect i on b i t lock (ppb lock) a glo ba l vol a t i le bi t . when s et to ?1?, the ppb s c a nnot b e ch a nged . when cle a red (?0?), the ppb s a re ch a nge ab le . there is only one ppb lock bi t per de- v i ce . the ppb lock is cle a red a fter power- u p or h a rd- w a re re s et . there is no comm a nd s e qu ence to u nlock the ppb lock . dynam i c protect i on b i t (dyb) a vol a t i le protect i on bi t is assi gned for e a ch s ector . after power- u p or h a rdw a re re s et, the content s of a ll dyb s is ?0? . e a ch dyb is i nd i v i d ua lly mod i f iab le thro u gh the dyb wr i te comm a nd . when the p a rt s a re f i r s t s h i pped, the ppb s a re cle a red, the dyb s a re cle a red, a nd ppb lock is de- f au lted to power u p i n the cle a red s t a te ? me a n i ng the ppb s a re ch a nge ab le . when the dev i ce is f i r s t powered on the dyb s power u p cle a red ( s ector s not protected) . the protect i on s t a te for e a ch s ector is determ i ned b y the log i c a l or of the ppb a nd the dyb rel a ted to th a t s ector . for the s ector s th a t h a ve the ppb s cle a red, the dyb s control whether or not the s ector is protected or u nprotected . by issui ng the dyb wr i te comm a nd s e qu ence s , the dyb s w i ll b e s et or cle a red, th us pl a c i ng e a ch s ector i n the protected or u nprotected s t a te . the s e a re the s o-c a lled dynam i c locked or unlocked s t a te s. they a re c a lled dyn a m i c s t a te s b ec aus e i t is very e as y to s w i tch ba ck a nd forth b etween the protected a nd u n- protected cond i t i on s. th is a llow s s oftw a re to e asi ly protect s ector s a g ai n s t i n a dvertent ch a nge s yet doe s not prevent the e as y remov a l of protect i on when ch a nge s a re needed . the dyb s m a y b e s et or cle a red as often as needed . the ppb s a llow for a more s t a t i c, a nd d i ff i c u lt to ch a nge, level of protect i on . the ppb s ret ai n the i r s t a te a cro ss power cycle s b ec aus e they a re non-vol a t i le . ind i v i d ua l ppb s a re s et w i th a comm a nd bu t m us t a ll b e cle a red as a gro u p thro u gh a complex s e qu ence of progr a m a nd er asi ng comm a nd s. the ppb s a re l i m- i ted to 100 er as e cycle s. the ppb lock bi t a dd s a n a dd i t i on a l level of protec- t i on . once a ll ppb s a re progr a mmed to the de si red s ett i ng s , the ppb lock m a y b e s et to ?1? . s ett i ng the ppb lock d isab le s a ll progr a m a nd er as e comm a nd s to the non-vol a t i le ppb s. in effect, the ppb lock b i t lock s the ppb s i nto the i r c u rrent s t a te . the only w a y to cle a r the ppb lock is to go thro u gh a power cycle . s y s tem b oot code c a n determ i ne i f a ny ch a nge s to the ppb a re needed e . g . to a llow new s y s tem code to b e downlo a ded . if no ch a nge s a re needed then the b oot code c a n s et the ppb lock to d isab le a ny f u rther ch a nge s to the ppb s d u r i ng s y s tem oper a t i on . the wp# wr i te protect p i n a dd s a f i n a l level of h a rd- w a re protect i on to the two o u termo s t 8 k b yte s s ector s i n the 75 % ba nk . when th is p i n is low i t is not po ssib le to ch a nge the content s of the s e two s ector s. it is po ssib le to h a ve s ector s th a t h a ve b een per sis - tently locked, a nd s ector s th a t a re left i n the dyn a m i c s t a te . the s ector s i n the dyn a m i c s t a te a re a ll u npro- tected . if there is a need to protect s ome of them, a si mple dyb wr i te comm a nd s e qu ence is a ll th a t is nece ssa ry . the dyb wr i te comm a nd for the dyn a m i c s ector s s w i tch the dyb s to si gn i fy protected a nd u n- protected, re s pect i vely . if there is a need to ch a nge the s t a t us of the per sis tently locked s ector s , a few more s tep s a re re qui red . f i r s t, the ppb lock bi t m us t b e d isab led b y e i ther p u tt i ng the dev i ce thro u gh a power-cycle, or h a rdw a re re s et . the ppb s c a n then b e ch a nged to reflect the de si red s ett i ng s. s ett i ng the ppb lock bi t once a g ai n w i ll lock the ppb s , a nd the dev i ce oper a te s norm a lly a g ai n . note : to a ch i eve the b e s t protect i on, i t? s recommended to exec u te the ppb lock bi t s et comm a nd e a rly i n the b oot code, a nd protect the b oot code b y hold i ng wp# = v il .
26 am29bdd160g june 7, 2006 table 11 .s ector protect i on s cheme s t ab le 11 cont ai n s a ll po ssib le com bi n a t i on s of the dyb, ppb, a nd ppb lock rel a t i ng to the s t a t us of the s ector . in su mm a ry, i f the ppb is s et, a nd the ppb lock is s et, the s ector is protected a nd the protect i on c a n not b e removed u nt i l the next power cycle cle a r s the ppb lock . if the ppb is cle a red, the s ector c a n b e dyn a m i - c a lly locked or u nlocked . the dyb then control s whether or not the s ector is protected or u nprotected . if the us er a ttempt s to progr a m or er as e a protected s ector, the dev i ce i gnore s the comm a nd a nd ret u rn s to re a d mode . a progr a m comm a nd to a protected s ector en ab le s s t a t us poll i ng for a pprox i m a tely 1 s b efore the dev i ce ret u rn s to re a d mode w i tho u t h a v i ng mod i - f i ed the content s of the protected s ector . an er as e comm a nd to a protected s ector en ab le s s t a t us poll i ng for a pprox i m a tely 50 s a fter wh i ch the dev i ce ret u rn s to re a d mode w i tho u t h a v i ng er as ed the protected s ec- tor . the progr a mm i ng of the dyb, ppb, a nd ppb lock for a g i ven s ector c a n b e ver i f i ed b y wr i t i ng a dyb/ppb/ppb lock ver i fy comm a nd to the dev i ce . per sis tent s ector protect i on mode lock i n g b i t l i ke the p ass word mode lock i ng bi t, a per sis tent s ec- tor protect i on mode lock i ng bi t ex is t s to g ua r a ntee th a t the dev i ce rem ai n i n s oftw a re s ector protect i on . once s et, the per sis tent s ector protect i on lock i ng bi t pre- vent s progr a mm i ng of the p ass word protect i on mode lock i ng bi t . th is g ua r a ntee s th a t a n u n au thor i zed us er co u ld not pl a ce the dev i ce i n p ass word protect i on mode . pa ss word protect i on mode the p ass word s ector protect i on mode method a llow s a n even h i gher level of s ec u r i ty th a n the per sis tent s ector protect i on mode . there a re two m ai n d i ffer- ence s b etween the per sis tent s ector protect i on a nd the p ass word s ector protect i on mode : when the dev i ce is f i r s t powered on, or come s o u t of a re s et cycle, the ppb lock bi t s et to the locked s tate , r a ther th a n cle a red to the u nlocked s t a te . the only me a n s to cle a r the ppb lock bi t is b y wr i t- i ng a u n iqu e 64-b i t pa ss word to the dev i ce . the p ass word s ector protect i on method is otherw is e i dent i c a l to the per sis tent s ector protect i on method . a 64- bi t p ass word is the only a dd i t i on a l tool u t i l i zed i n th is method . the p ass word is s tored i n a one-t i me pro g rammable (otp) reg i on of the fl as h memory . once the p ass word mode lock i ng b i t is s et, the p ass word is perm a nently s et w i th no me a n s to re a d, progr a m, or er as e i t . the p ass word is us ed to cle a r the ppb lock bi t . the p ass - word unlock comm a nd m us t b e wr i tten to the fl as h, a long w i th a p ass word . the fl as h dev i ce i ntern a lly comp a re s the g i ven p ass word w i th the pre-pro- gr a mmed p ass word . if they m a tch, the ppb lock bi t is cle a red, a nd the ppb s c a n b e a ltered . if they do not m a tch, the fl as h dev i ce doe s noth i ng . there is a bui lt- i n 2 s del a y for e a ch ?p ass word check . ? th is del a y is i ntended to thw a rt a ny effort s to r u n a progr a m th a t tr i e s a ll po ssib le com bi n a t i on s i n order to cr a ck the p ass word . pa ss word and pa ss word mode lock i n g b i t in order to s elect the p ass word s ector protect i on s cheme, the c us tomer m us t f i r s t progr a m the p ass - word . one method of choo si ng a p ass word wo u ld b e to correl a te i t to the u n iqu e electron i c s er ia l n u m b er (e s n) of the p a rt i c u l a r fl as h dev i ce . another method co u ld gener a te a d a t abas e where a ll the p ass word s a re s tored, e a ch of wh i ch correl a te s to a s er ia l n u m b er on the dev i ce . e a ch e s n is d i fferent for every fl as h dev i ce ; therefore e a ch p ass word s ho u ld b e d i fferent for every fl as h dev i ce . wh i le progr a mm i ng i n the p ass - word reg i on, the c us tomer m a y perform p ass word ver i fy oper a t i on s. once the de si red p ass word is progr a mmed i n, the c us tomer m us t then s et the p ass word mode lock i ng b i t . th is oper a t i on a ch i eve s two o bj ect i ve s: dyb ppb ppb lock s ector s tate 000 unprotected?ppb a nd dyb a re ch a nge ab le 001 unprotected?ppb not ch a nge ab le, dyb is ch a nge ab le 010 protected?ppb a nd dyb a re ch a nge ab le 100 110 011 protected?ppb not ch a nge ab le, dyb is ch a nge ab le 101 111
june 7, 2006 am29bdd160g 27 1 . it perm a nently s et s the dev i ce to oper a te usi ng the p ass word protect i on mode . it is not po ssib le to re- ver s e th is f u nct i on . 2 . it a l s o d isab le s a ll f u rther comm a nd s to the p ass - word reg i on . all progr a m, a nd re a d oper a t i on s a re i gnored . both of the s e o bj ect i ve s a re i mport a nt, a nd i f not c a re- f u lly con si dered, m a y le a d to u nrecover ab le error s. the us er m us t b e su re th a t the p ass word protect i on method is de si red when s ett i ng the p ass word mode lock i ng b i t . more i mport a ntly, the us er m us t b e su re th a t the p ass word is correct when the p ass word mode lock i ng b i t is s et . d u e to the f a ct th a t re a d oper a t i on s a re d isab led, there is no me a n s to ver i fy wh a t the p ass word is a fterw a rd s. if the p ass word is lo s t a fter s ett i ng the p ass word mode lock i ng b i t, there w i ll b e no w a y to cle a r the ppb lock bi t . the p ass word mode lock i ng b i t, once s et, prevent s re a d i ng the 64- bi t p ass word on the dq bus a nd f u rther p ass word progr a mm i ng . the p ass word mode lock i ng b i t is not er asab le . once p ass word mode lock i ng b i t is progr a mmed, the per sis tent s ector protect i on lock- i ng b i t is d isab led from progr a mm i ng, g ua r a ntee i ng th a t no ch a nge s to the protect i on s cheme a re a llowed . 64-b i t pa ss word the 64- bi t p ass word is loc a ted i n i t s own memory s p a ce a nd is a cce ssib le thro u gh the us e of the p ass - word progr a m a nd ver i fy comm a nd s ( s ee p ass word ver i fy comm a nd ) . the p ass word f u nct i on work s i n con ju nct i on w i th the p ass word mode lock i ng b i t, wh i ch when s et, prevent s the p ass word ver i fy com- m a nd from re a d i ng the content s of the p ass word on the p i n s of the dev i ce . wr i te protect (wp#) the dev i ce fe a t u re s a h a rdw a re protect i on opt i on usi ng a wr i te protect p i n th a t prevent s progr a mm i ng or er asi ng, reg a rdle ss of the s t a te of the s ector? s per sis - tent or dyn a m i c protect i on b i t s. the wp# p i n is ass o- c ia ted w i th the two o u termo s t 8 k b yte s s ector s i n the 75 % ba nk . the wp# p i n h as no effect on a ny other s ector . when wp# is t a ken to v il , progr a mm i ng a nd er as e oper a t i on s of the two o u termo s t 8 k b yte s s ec- tor s i n the 75 % ba nk a re d isab led . by t a k i ng wp# ba ck to v ih , the two o u termo s t 8 k b yte s s ector s a re en ab led for progr a m a nd er as e oper a t i on s , depend i ng u pon the s t a t us of the i nd i v i d ua l s ector per sis tent or dyn a m i c protect i on b i t s. if e i ther of the two o u termo s t s ector s per sis tent or dyn a m i c protect i on b i t s a re pro- gr a mmed, progr a m or er as e oper a t i on s a re i nh ibi ted . if the s ector per sis tent or dyn a m i c protect i on b i t s a re b oth er as ed, the two s ector s a re a v ai l ab le for pro- gr a mm i ng or er asi ng as long as wp# rem ai n s a t v ih . the us er m us t hold the wp# p i n a t e i ther v ih or v il d u r i ng the ent i re progr a m or er as e oper a t i on of the two o u termo s t s ector s i n the 75 % ba nk . s ec si ? ( s ecured si l i con) s ector protect i on the s ec si s ector is a 256- b yte fl as h memory a re a th a t is e i ther progr a mm ab le a t the c us tomer or b y amd a t the re qu e s t of the c us tomer . the s ec si s ector entry comm a nd en ab le s the ho s t s y s tem to a ddre ss the s ec si s ector for progr a mm i ng or re a d i ng . the s ec si s ector a ddre ss r a nge is 00000h?000 3 fh for the top b oot b lock conf i g u r a t i on a nd 7ffc0h?7ffffh for the b ottom b oot b lock conf i g u r a t i on . addre ss r a nge 00040h?007ffh for the top b oot b lock a nd 7f 8 00h?7ffbfh ret u rn i nv a l i d d a t a when a ddre ss ed w i th the s ec si s ector en ab led . unl i ke prev i o us fl as h memory dev i ce s , the am2 9 bdd160 a llow s si m u lt a neo us oper a t i on wh i le the s ec si s ector is en ab led . however, there a re a n u m b er of re s tr i ct i on s ass oc ia ted w i th si m u lt a neo us oper a t i on a nd dev i ce oper a t i on when the s ec si s ector is en ab led : 1 . the s ec si s ector is not a v ai l ab le for re a d i ng wh i le the p ass word unlock, a ny ppb progr a m/er as e op- er a t i on, or p ass word progr a mm i ng a re i n progre ss. re a d i ng to a ny loc a t i on i n the s m a ll (25 % ) s ector w i ll ret u rn the s t a t us of the s e oper a t i on s u nt i l the s e oper a t i on s h a ve completed exec u t i on . 2 . wr i t i ng the corre s pond i ng dyb ass oc ia ted w i th the overl ai d b oot b lock s ector re su lt s i n the dyb not b e i ng u pd a ted . th is is only a ccompl is hed when the s ec si s ector is not en ab led . 3. re a d i ng the corre s pond i ng dyb ass oc ia ted w i th the overl ai d b oot b lock s ector re su lt s i n re a d i ng i n- v a l i d d a t a when the ppb lock/dyb ver i fy com- m a nd is issu ed . th is f u nct i on is only a ccompl is hed when the s ec si s ector is not en ab led . 4 . all comm a nd s a re a v ai l ab le for exec u t i on when the s ec si s ector is en ab led except the follow i ng l is t . i s - sui ng the follow i ng comm a nd s wh i le the s ec si s ec- tor is en ab led re su lt s i n the comm a nd b e i ng i gnored . all unlock byp ass comm a nd s cfi acceler a ted progr a m progr a m a nd s ector er as e sus pend progr a m a nd s ector er as e re su me 5 . exec u t i ng the s ector er as e comm a nd is perm i tted when the s ec si s ector is en ab led, however, there is no prov isi on for er asi ng the s ec si s ector w i th the s ector er as e comm a nd, reg a rdle ss of the protec- t i on s t a t us. the s ector er as e comm a nd w i ll er as e a ll other s ector s when the s ec si s ector is en ab led .
28 am29bdd160g june 7, 2006 6 . exec u t i ng the ch i p er as e comm a nd is perm i tted when the s ec si s ector is en ab led . the ch i p er as e comm a nd er as e s a ll s ector s i n the memory a rr a y except for s ector 0 i n top- b oot b lock conf i g u r a t i on a nd s ector 45 i n b ottom- b oot b lock conf i g u r a t i on . the s ec si s ector is a one-t i me progr a mm ab le memory a re a th a t c a nnot b e er as ed . 7 . exec u t i ng the s ec si s ector entry comm a nd d u r i ng progr a m or er as e sus pend mode is a llowed . the s ector er as e/progr a m re su me comm a nd is d is - ab led wh i le the s ec si s ector is en ab led, a nd the us er c a nnot re su me progr a mm i ng of the memory a rr a y u nt i l the ex i t s ec si s ector comm a nd is wr i t- ten . s ec si s ector protect i on b i t the s ec si s ector protect i on b i t prevent s progr a m- m i ng of the s ec si s ector memory a re a. once s et, the s ec si s ector memory a re a content s a re non-mod i f i - ab le . per sis tent protect i on b i t lock the per sis tent protect i on b i t (ppb) lock is a vol a t i le bi t th a t reflect s the s t a te of the p ass word mode lock- i ng b i t a fter power- u p re s et . if the p ass word mode lock i ng b i t is s et, wh i ch i nd i c a te s the dev i ce is i n p ass word protect i on mode, the ppb lock b i t is a l s o s et a fter a h a rdw a re re s et (re s et# ass erted) or a power- u p re s et . the only me a n s for cle a r i ng the ppb lock b i t i n p ass word protect i on mode is to issu e the p ass word unlock comm a nd . su cce ss f u l exec u t i on of the p ass word unlock comm a nd cle a r s the ppb lock b i t, a llow i ng for s ector ppb s mod i f i c a t i on s. a s - s ert i ng re s et#, t a k i ng the dev i ce thro u gh a power-on re s et, or issui ng the ppb lock b i t s et comm a nd s et s the ppb lock b i t ba ck to a ?1? . if the p ass word mode lock i ng b i t is not s et, i nd i c a t i ng per sis tent s ector protect i on mode, the ppb lock b i t is cle a red a fter power- u p or h a rdw a re re s et . the ppb lock b i t is s et b y issui ng the ppb lock b i t s et com- m a nd . once s et the only me a n s for cle a r i ng the ppb lock b i t is b y issui ng a h a rdw a re or power- u p re s et . the p ass word unlock comm a nd is i gnored i n per sis - tent s ector protect i on mode . hardware data protect i on the comm a nd s e qu ence re qui rement of u nlock cycle s for progr a mm i ng or er asi ng prov i de s d a t a protect i on a g ai n s t i n a dvertent wr i te s. in a dd i t i on, the follow i ng h a rdw a re d a t a protect i on me asu re s prevent a cc i dent a l er asu re or progr a mm i ng, wh i ch m i ght otherw is e b e c aus ed b y s p u r i o us s y s tem level si gn a l s d u r i ng v cc power- u p a nd power-down tr a n si t i on s , or from s y s tem no is e . low v cc wr i te inh i b i t when v cc is le ss th a n v lko , the dev i ce doe s not a c- cept a ny wr i te cycle s. th is protect s d a t a d u r i ng v cc power- u p a nd power-down . the comm a nd reg is ter a nd a ll i ntern a l er as e/progr a m c i rc ui t s a re d isab led, a nd the dev i ce re s et s. subs e qu ent wr i te s a re i gnored u nt i l v cc is gre a ter th a n v lko . the s y s tem m us t pro- v i de the proper si gn a l s to the control p i n s to prevent u n i ntent i on a l wr i te s when v cc is gre a ter th a n v lko . wr i te pul s e ?gl i tch? protect i on no is e p u l s e s of le ss th a n 5 n s (typ i c a l) on oe#, ce#, or we# do not i n i t ia te a wr i te cycle . lo gi cal inh i b i t wr i te cycle s a re i nh ibi ted b y hold i ng a ny one of oe# = v il , ce# = v ih , or we# = v ih . to i n i t ia te a wr i te cycle, ce# a nd we# m us t b e a log i c a l zero (v il ) wh i le oe# is a log i c a l one (v ih ) . power-up wr i te inh i b i t if we# = ce# = v il a nd oe# = v ih d u r i ng power- u p, the dev i ce doe s not a ccept comm a nd s on the r isi ng edge of we# . the i ntern a l s t a te m a ch i ne is au tom a t i - c a lly re s et to re a d i ng a rr a y d a t a on power- u p . v cc and v io power-up and power-down s equenc i n g the dev i ce i mpo s e s no re s tr i ct i on s on v cc a nd v io power- u p or power-down s e qu enc i ng . a ss ert i ng re- s et# to v il is re qui red d u r i ng the ent i re v cc a nd v io power s e qu ence u nt i l the re s pect i ve su ppl i e s re a ch the i r oper a t i ng volt a ge s. once, v cc a nd v io a tt ai n the i r re s pect i ve oper a t i ng volt a ge s , de- ass ert i on of re- s et# to v ih is perm i tted .
june 7, 2006 am29bdd160g 29 notes: 1 . secs i sector overl a y s th is s ector when en ab led . 2 . the ba nk a ddre ss is determ i ned b y a18 a nd a17 . ba = 00 for b a nk 1 a nd ba = 01, 10, or 11 for b a nk 2 . 3 . th is s ector h as the a dd i t i on a l wp# p i n s ector protect i on fe a t u re . table 12 .s ector addre ss e s for top boot s ector dev i ce s s ector s ector group x16 addre ss ran g e (a1 8 :a-1) x 3 2 addre ss ran g e (a1 8 :a0) s ector si ze (kword s ) bank 1 (note 2) s a0 (note 1) s g0 00000h-00fffh 00000h-007ffh 4 s a1 s g1 01000h-01fffh 00 8 00h-00fffh 4 s a2 s g2 02000h-02fffh 01000h-017ffh 4 s a 3s g 3 0 3 000h-0 3 fffh 01 8 00h-01fffh 4 s a4 s g4 04000h-04fffh 02000h-027ffh 4 s a5 s g5 05000h-05fffh 02 8 00h-02fffh 4 s a6 s g6 06000h-06fffh 0 3 000h-0 3 7ffh 4 s a7 s g7 07000h-07fffh 0 38 00h-0 3 fffh 4 s a 8 s g 8 0 8 000h-0ffffh 04000h-07fffh 3 2 s a 9 10000h-17fffh 0 8 000h-0bfffh 3 2 s a10 1 8 000h-1ffffh 0c000h-0ffffh 3 2 s a11 s g 9 20000h-27fffh 10000h-1 3 fffh 3 2 s a12 2 8 000h-2ffffh 14000h-17fffh 3 2 s a1 33 0000h- 3 7fffh 1 8 000h-1bfffh 3 2 s a14 38 000h- 3 ffffh 1c000h-1ffffh 3 2 bank 2 (note 2) s a15 s g10 40000h-47fffh 20000h-2 3 fffh 3 2 s a16 4 8 000h-4ffffh 24000h-27fffh 3 2 s a17 50000h-57fffh 2 8 000h-2bfffh 3 2 s a1 8 5 8 000h-5ffffh 2c000h-2ffffh 3 2 s a1 9 s g11 60000h-67fffh 3 0000h- 33 fffh 3 2 s a20 6 8 000h-6ffffh 3 4000h- 3 7fffh 3 2 s a21 70000h-77fffh 38 000h- 3 bfffh 3 2 s a22 7 8 000h-7ffffh 3 c000h- 3 ffffh 3 2 s a2 3 s g12 8 0000h- 8 7fffh 40000h-4 3 fffh 3 2 s a24 88 000h- 8 ffffh 44000h-47fffh 3 2 s a25 9 0000h- 9 7fffh 4 8 000h-4bfffh 3 2 s a26 98 000h- 9 ffffh 4c000h-4ffffh 3 2 s a27 s g1 3 a0000h-a7fffh 50000h-5 3 fffh 3 2 s a2 8 a 8 000h-affffh 54000h-57fffh 3 2 s a2 9 b0000h-b7fffh 5 8 000h-5bfffh 3 2 s a 3 0b 8 000h-bffffh 5c000h-5ffffh 3 2 s a 3 1 s g14 c0000h-c7fffh 60000h-6 3 fffh 3 2 s a 3 2c 8 000h-cffffh 64000h-67fffh 3 2 s a 33 d0000h-d7fffh 6 8 000h-6bfffh 3 2 s a 3 4d 8 000h-dffffh 6c000h-6ffffh 3 2 s a 3 5 s g15 e0000h-e7fffh 70000h-7 3 fffh 3 2 s a 3 6e 8 000h-effffh 74000h-77fffh 3 2 s a 3 7 f0000h-f7fffh 7 8 000h-7bfffh 3 2 s a 38 s g16 f 8 000h-f 8 fffh 7c000h-7c7ffh 4 s a 39 s g17 f 9 000h-f 9 fffh 7c 8 00h-7cfffh 4 s a40 s g1 8 fa000h-fafffh 7d000h-7d7ffh 4 s a41 s g1 9 fb000h-fbfffh 7d 8 00h-7dfffh 4 s a42 s g20 fc000h-fcfffh 7e000h-7e7ffh 4 s a4 3s g21 fd000h-fdfffh 7e 8 00h-7efffh 4 s a44 (note 3 ) s g22 fe000h-fefffh 7f000h-7f7ffh 4 s a45 (note 3 ) s g2 3 ff000h-fffffh 7f 8 00h-7ffffh 4
30 am29bdd160g june 7, 2006 notes: 1 . th is s ector h as the a dd i t i on a l wp# p i n s ector protect i on fe a t u re . 2 . the ba nk a ddre ss is determ i ned b y a18 a nd a17 . ba = 00, 01, or 10 for b a nk 1 a nd ba = 11 for b a nk 2 . 3 . secs i sector overl a y s th is s ector when en ab led . table 1 3. s ector addre ss e s for bottom boot s ector dev i ce s s ector s ector group x16 addre ss ran g e (a1 8 :a-1) x 3 2 addre ss ran g e (a1 8 :a0) s ector si ze (kword s ) bank 1 (note 2) s a0 (note 1) s g0 00000h-00fffh 00000h-007ffh 4 s a1 (note 1) s g1 01000h-01fffh 00 8 00h-00fffh 4 s a2 s g2 02000h-02fffh 01000h-017ffh 4 s a 3s g 3 0 3 000h-0 3 fffh 01 8 00h-01fffh 4 s a4 s g4 04000h-04fffh 02000h-027ffh 4 s a5 s g5 05000h-05fffh 02 8 00h-02fffh 4 s a6 s g6 06000h-06fffh 0 3 000h-0 3 7ffh 4 s a7 s g7 07000h-07fffh 0 38 00h-0 3 fffh 4 s a 8 s g 8 0 8 000h-0ffffh 04000h-07fffh 3 2 s a 9 10000h-17fffh 0 8 000h-0bfffh 3 2 s a10 1 8 000h-1ffffh 0c000h-0ffffh 3 2 s a11 s g 9 20000h-27fffh 10000h-1 3 fffh 3 2 s a12 2 8 000h-2ffffh 14000h-17fffh 3 2 s a1 33 0000h- 3 7fffh 1 8 000h-1bfffh 3 2 s a14 38 000h- 3 ffffh 1c000h-1ffffh 3 2 s a15 s g10 40000h-47fffh 20000h-2 3 fffh 3 2 s a16 4 8 000h-4ffffh 24000h-27fffh 3 2 s a17 50000h-57fffh 2 8 000h-2bfffh 3 2 s a1 8 5 8 000h-5ffffh 2c000h-2ffffh 3 2 s a1 9 s g11 60000h-67fffh 3 0000h- 33 fffh 3 2 s a20 6 8 000h-6ffffh 3 4000h- 3 7fffh 3 2 s a21 70000h-77fffh 38 000h- 3 bfffh 3 2 s a22 7 8 000h-7ffffh 3 c000h- 3 ffffh 3 2 s a2 3 s g12 8 0000h- 8 7fffh 40000h-4 3 fffh 3 2 s a24 88 000h- 8 ffffh 44000h-47fffh 3 2 s a25 9 0000h- 9 7fffh 4 8 000h-4bfffh 3 2 s a26 98 000h- 9 ffffh 4c000h-4ffffh 3 2 s a27 s g1 3 a0000h-a7fffh 50000h-5 3 fffh 3 2 s a2 8 a 8 000h-affffh 54000h-57fffh 3 2 s a2 9 b0000h-b7fffh 5 8 000h-5bfffh 3 2 s a 3 0b 8 000h-bffffh 5c000h-5ffffh 3 2 bank 2 (note 2) s a 3 1 s g14 c0000h-c7fffh 60000h-6 3 fffh 3 2 s a 3 2c 8 000h-cffffh 64000h-67fffh 3 2 s a 33 d0000h-d7fffh 6 8 000h-6bfffh 3 2 s a 3 4d 8 000h-dffffh 6c000h-6ffffh 3 2 s a 3 5 s g15 e0000h-e7fffh 70000h-7 3 fffh 3 2 s a 3 6e 8 000h-effffh 74000h-77fffh 3 2 s a 3 7 f0000h-f7fffh 7 8 000h-7bfffh 3 2 s a 38 s g16 f 8 000h-f 8 fffh 7c000h-7c7ffh 4 s a 39 s g17 f 9 000h-f 9 fffh 7c 8 00h-7cfffh 4 s a40 s g1 8 fa000h-fafffh 7d000h-7d7ffh 4 s a41 s g1 9 fb000h-fbfffh 7d 8 00h-7dfffh 4 s a42 s g20 fc000h-fcfffh 7e000h-7e7ffh 4 s a4 3s g21 fd000h-fdfffh 7e 8 00h-7efffh 4 s a44 s g22 fe000h-fefffh 7f000h-7f7ffh 4 s a45 (note 3 ) s g2 3 ff000h-fffffh 7f 8 00h-7ffffh 4
june 7, 2006 am29bdd160g 31 common fla s h memory interface (cfi) the common fl as h interf a ce (cfi) s pec i f i c a t i on o u t- l i ne s dev i ce a nd ho s t s y s tem s oftw a re i nterrog a t i on h a nd s h a ke, wh i ch a llow s s pec i f i c vendor- s pec i f i ed s oftw a re a lgor i thm s to b e us ed for ent i re f a m i l i e s of dev i ce s. s oftw a re su pport c a n then b e dev i ce- i nde- pendent, jedec id- i ndependent, a nd forw a rd- a nd ba ckw a rd-comp a t ib le for the s pec i f i ed fl as h dev i ce f a m i l i e s. fl as h vendor s c a n s t a nd a rd i ze the i r ex is t i ng i nterf a ce s for long-term comp a t ibi l i ty . th is dev i ce enter s the cfi q u ery mode when the s y s - tem wr i te s the cfi q u ery comm a nd, 98 h, to a ddre ss 55h i n word mode (or a ddre ss aah i n b yte mode), a ny t i me the dev i ce is re a dy to re a d a rr a y d a t a. the s y s tem c a n re a d cfi i nform a t i on a t the a ddre ss e s g i ven i n t ab le s 1 3 ?16 . to term i n a te re a d i ng cfi d a t a , the s y s tem m us t wr i te the re s et comm a nd . the s y s tem c a n a l s o wr i te the cfi qu ery comm a nd when the dev i ce is i n the au to s elect mode . the dev i ce enter s the cfi qu ery mode, a nd the s y s tem c a n re a d cfi d a t a a t the a ddre ss e s g i ven i n t ab le s 1 3 ?16 . the s y s tem m us t wr i te the re s et comm a nd to ret u rn the de- v i ce to the au to s elect mode . for f u rther i nform a t i on, ple as e refer to the cfi s pec i f i - c a t i on a nd cfi p ub l i c a t i on 100, a v ai l ab le v ia the world w i de we b a t http : //www .a md . com/prod- u ct s /nvd/overv i ew/cf i. html . altern a t i vely, cont a ct a n amd repre s ent a t i ve for cop i e s of the s e doc u ment s. table 14 . cfi query ident i f i cat i on s tr i n g table 15 . cfi s y s tem interface s tr i n g addre ss e s (x 3 2 mode) addre ss e s (x16 mode) data de s cr i pt i on 10h 11h 12h 20h 22h 24h 0051h 0052h 005 9 h q u ery un iqu e a s cii s tr i ng ?qry? 1 3 h 14h 26h 2 8 h 0002h 0000h pr i m a ry oem comm a nd s et 15h 16h 2ah 2ch 0040h 0000h addre ss for pr i m a ry extended t ab le 17h 1 8 h 2eh 3 0h 0000h 0000h altern a te oem comm a nd s et (00h = none ex is t s ) 1 9 h 1ah 3 2h 3 4h 0000h 0000h addre ss for altern a te oem extended t ab le (00h = none ex is t s ) addre ss e s (x 3 2 mode) addre ss e s (x16 mode) data de s cr i pt i on 1bh 3 6h 002 3 h v cc m i n . (wr i te/er as e) dq7?dq4 : volt s , dq 3 ?dq0 : 100 m i ll i volt 1ch 38 h 0027h v cc m a x . (wr i te/er as e) dq7?dq4 : volt s , dq 3 ?dq0 : 100 m i ll i volt 1dh 3 ah 0000h v pp m i n . volt a ge (00h = no v pp p i n pre s ent) 1eh 3 ch 0000h v pp m a x . volt a ge (00h = no v pp p i n pre s ent) 1fh 3 eh 0004h typ i c a l t i meo u t per si ngle word/do ub leword progr a m 2 n s 20h 40h 0000h typ i c a l t i meo u t for m i n . si ze bu ffer progr a m 2 n s (00h = not su pported) 21h 42h 000 9 htyp i c a l t i meo u t per i nd i v i d ua l b lock er as e 2 n m s 22h 44h 0000h typ i c a l t i meo u t for f u ll ch i p er as e 2 n m s (00h = not su pported) 2 3 h 46h 0005h m a x . t i meo u t for word/do ub leword progr a m 2 n t i me s typ i c a l 24h 4 8 h 0000h m a x . t i meo u t for bu ffer wr i te 2 n t i me s typ i c a l 25h 4ah 0007h m a x . t i meo u t per i nd i v i d ua l b lock er as e 2 n t i me s typ i c a l 26h 4ch 0000h m a x . t i meo u t for f u ll ch i p er as e 2 n t i me s typ i c a l (00h = not su pported)
32 am29bdd160g june 7, 2006 table 16 . cfi dev i ce geometry def i n i t i on addre ss e s (x 3 2 mode) addre ss e s (x16 mode) data de s cr i pt i on 27h 4eh 0015h dev i ce si ze = 2 n b yte 2 8 h 2 9 h 50h 52h 0005h 0000h fl as h dev i ce interf a ce de s cr i pt i on (for complete de s cr i pt i on, ple as e refer to cfi p ub l i c a t i on 100) 0000 = x 8 -only as ynchrono us i nterf a ce 0001 = x16-only as ynchrono us i nterf a ce 0002 = su pport s x 8 a nd x16 v ia byte# w i th as ynchrono us i nterf a ce 000 3 = x 3 2-only as ynchrono us i nterf a ce 0005 = su pport s x16 a nd x 3 2 v ia word# w i th as ynchrono us i nterf a ce 2ah 2bh 54h 56h 0000h 0000h m a x . n u m b er of b yte i n m u lt i - b yte progr a m = 2 n (00h = not su pported) 2ch 5 8 h 000 3 h 0004h n u m b er of er as e block reg i on s w i th i n dev i ce 000 3 = s peed opt i on s 54d, 65d, 65a 2dh 2eh 2fh 3 0h 5ah 5ch 5eh 60h 0007h 0000h 0020h 0000h er as e block reg i on 1 inform a t i on (refer to the cfi s pec i f i c a t i on or cfi p ub l i c a t i on 100) 3 1h 3 2h 33 h 3 4h 62h 64h 66h 6 8 h 001dh 0000h 0000h 0001h er as e block reg i on 2 inform a t i on (refer to the cfi s pec i f i c a t i on or cfi p ub l i c a t i on 100) 3 5h 3 6h 3 7h 38 h 6ah 6ch 6eh 70h 0007h 0000h 0020h 0000h er as e block reg i on 3 inform a t i on (refer to the cfi s pec i f i c a t i on or cfi p ub l i c a t i on 100) 39 h 3 ah 3 bh 3 ch 72h 74h 76h 7 8 h 0000h 0000h 0000h 0000h er as e block reg i on 4 inform a t i on (refer to the cfi s pec i f i c a t i on or cfi p ub l i c a t i on 100) table 17 . cfi pr i mary vendor- s pec i f i c extended query addre ss e s (x 3 2 mode) addre ss e s (x16 mode) data de s cr i pt i on 40h 41h 42h 8 0h 8 2h 8 4h 0050h 0052h 004 9 h q u ery- u n iqu e a s cii s tr i ng ?pri? 4 3 h 8 6h 00 3 1h m aj or ver si on n u m b er, a s cii (reflect s mod i f i c a t i on s to the si l i con) 44h 88 h00 33 hm i nor ver si on n u m b er, a s cii (reflect s mod i f i c a t i on s to the cfi t ab le) 45h 8 ah 0004h addre ss s en si t i ve unlock (dq1, dq0) 00 = re qui red, 01 = not re qui red si l i con rev isi on n u m b er (dq5?dq2 0000 = c s 4 9 0001 = c s 5 9 0010 = c s99 0011 = c s 6 9 0100 = c s 11 9
june 7, 2006 am29bdd160g 33 46h 8 ch 0002h er as e sus pend (1 b yte) 00 = not su pported 01 = to re a d only 02 = to re a d a nd wr i te 47h 8 eh 0001h s ector protect (1 b yte) 00 = not su pported, x = n u m b er of s ector s i n per gro u p 4 8 h 9 0h 0000h te m p o r a ry s ector unprotect 00h = not su pported, 01h = su pported 4 9 h 9 2h 0006h s ector protect/unprotect s cheme (1 b yte) 01 =2 9 f040 mode, 02 = 2 9 f016 mode 0 3 = 2 9 f400 mode, 04 = 2 9 lv 8 00 mode 05 = 2 9 bd s 640 mode ( s oftw a re comm a nd lock i ng) 06 = bdd160 mode (new s ector protect) 07 = 2 9 lv 8 00 + pdl12 8 (new s ector protect) mode 4ah 9 4h 001fh si m u lt a neo us oper a t i on (1 b yte) 00h = not su pported, x = n u m b er of s ector s i n a ll ba nk s except b a nk 1 4bh 9 6h 0001h b u r s t mode type 00h = not su pported, 01h = su pported 4ch 98 h 0000h p a ge mode type 00h = not su pported, 01h = 4 word p a ge, 02h = 8 word p a ge 4dh 9 ah 00b5h acc (acceler a t i on) su pply m i n i m u m 00h = not su pported (dq7-dq4 : volt i n hex, dq 3 -dq0 : 100 mv i n bcd) 4eh 9 ch 00c5h acc (acceler a t i on) su pply m a x i m u m 00h = not su pported, (dq7-dq4 : volt i n hex, dq 3 -dq0 : 100 mv i n bcd) 4fh 9 eh 0001h top/bottom boot s ector fl a g (1 b yte) 00h = un i form dev i ce, no wp# control, 01h = 8 x 8 k b s ector s a t top a nd b ottom w i th wp# control 02h = bottom b oot dev i ce 0 3 h = top b oot dev i ce 04h = un i form, bottom wp# protect 05h = un i form, top wp# protect if the n u m b er of er as e b lock reg i on s = 1, then i gnore th is f i eld 50h a0h 0001h progr a m sus pend 00 = not su pported 01 = su pported 51h a2h 0000h wr i te b u ffer si ze 2 (n+1) word( s ) 57h aeh 0002h b a nk org a n i z a t i on (1 b yte) 00 = if d a t a a t 4ah is zero xx = n u m b er of ba nk s 5 8 h b0h 000fh b a nk 1 reg i on inform a t i on (1 b yte) xx = n u m b er of s ector s i n b a nk 1 5 9 h b2h 001fh b a nk 2 reg i on inform a t i on (1 b yte) xx = n u m b er of s ector s i n b a nk 2 5ah b4h 0000h b a nk 3 reg i on inform a t i on (1 b yte) xx = n u m b er of s ector s i n b a nk 3 5bh b6h 0000h b a nk 4 reg i on inform a t i on (1 b yte) xx = n u m b er of s ector s i n b a nk 4 table 17 . cfi pr i mary vendor- s pec i f i c extended query (cont i nued) addre ss e s (x 3 2 mode) addre ss e s (x16 mode) data de s cr i pt i on
34 am29bdd160g june 7, 2006 command definition s wr i t i ng s pec i f i c a ddre ss a nd d a t a comm a nd s or s e- qu ence s i nto the comm a nd reg is ter i n i t ia te s dev i ce op- er a t i on s. t ab le s 1 8 -21 def i ne the v a l i d reg is ter comm a nd s e qu ence s. wr i t i ng i ncorrect addre ss and data value s or wr i t i ng them i n the i mproper s e- quence re s et s the dev i ce to re a d i ng a rr a y d a t a. all a ddre ss e s a re l a tched on the f a ll i ng edge of we# or ce#, wh i chever h a ppen s l a ter . all d a t a is l a tched on the r isi ng edge of we# or ce#, wh i chever h a ppen s f i r s t . refer to the ac ch a r a cter is t i c s s ect i on for t i m i ng d ia gr a m s. read i n g array data i n non-bur s t mode the dev i ce is au tom a t i c a lly s et to re a d i ng a rr a y d a t a a fter dev i ce power- u p . no comm a nd s a re re qui red to retr i eve d a t a. the dev i ce is a l s o re a dy to re a d a rr a y d a t a a fter complet i ng a n em b edded progr a m or em- b edded er as e a lgor i thm . after the dev i ce a ccept s a n er as e sus pend com- m a nd, the dev i ce enter s the er as e sus pend mode . the s y s tem c a n re a d a rr a y d a t a usi ng the s t a nd a rd re a d t i m i ng s , except th a t i f i t re a d s a t a n a ddre ss w i th i n er as e- sus pended s ector s , the dev i ce o u tp u t s s t a t us d a t a. after complet i ng a progr a mm i ng oper a - t i on i n the er as e sus pend mode, the s y s tem m a y once a g ai n re a d a rr a y d a t a w i th the sa me except i on . s ee s ector er as e a nd progr a m sus pend comm a nd for more i nform a t i on on th is mode . the s y s tem m us t issu e the re s et comm a nd to re-en- ab le the dev i ce for re a d i ng a rr a y d a t a i f dq5 goe s h i gh, or wh i le i n the au to s elect mode . s ee the the progr a m- m i ng of the ppb lock b i t for a g i ven s ector c a n b e ver- i f i ed b y wr i t i ng a ppb lock b i t s t a t us ver i fy comm a nd to the dev i ce . s ect i on . s ee a l s o a s ynchrono us re a d oper a t i on (non-b u r s t) i n the key to s w i tch i ng w a veform s s ect i on for more i nform a t i on . s ee the s ector er as e a nd progr a m re su me comm a nd s ect i on s for more i nform a t i on on th is mode . read i n g array data i n bur s t mode the dev i ce is c a p ab le of very f as t b u r s t mode re a d op- er a t i on s. the conf i g u r a t i on reg is ter s et s the re a d con- f i g u r a t i on, bu r s t order, fre qu ency conf i g u r a t i on, a nd bu r s t length . upon power on, the dev i ce def au lt s to the as ynchro- no us mode . in th is mode, clk, a nd adv# a re i gnored . the dev i ce oper a te s l i ke a convent i on a l fl as h dev i ce . d a t a is a v ai l ab le t acc /t ce n a no s econd s a fter a ddre ss b ecome s s t ab le, ce# b ecome ass erted . the dev i ce enter s the bu r s t mode b y en ab l i ng s ynchrono us bu r s t re a d s i n the conf i g u r a t i on reg is ter . the dev i ce ex i t s bu r s t mode b y d isab l i ng s ynchrono us bu r s t re a d s i n the conf i g u r a t i on reg is ter . ( s ee comm a nd def i n i t i on s ) . the re s et# comm a nd w i ll not term i n a te the b u r s t mode . s y s tem re s et (power on re s et) w i ll term i n a te the b u r s t mode . the dev i ce h as the reg u l a r control p i n s , i. e . ch i p en- ab le (ce#), wr i te en ab le (we#), a nd o u tp u t en ab le (oe#) to control norm a l re a d a nd wr i te oper a t i on s. moreover, three a dd i t i on a l control p i n s h a ve b een a dded to a llow e as y i nterf a ce w i th m i n i m a l gl u e log i c to a w i de r a nge of m i croproce ss or s / m i crocontroller s for h i gh perform a nce b u r s t re a d c a p abi l i ty . the s e a d- d i t i on a l p i n s a re addre ss v a l i d (adv#) a nd clock (clk) . ce#, oe#, a nd we# a re as ynchrono us (rel a - t i ve to clk) . the b u r s t mode re a d oper a t i on is a s yn- chrono us oper a t i on t i ed to the edge of the clock . the m i croproce ss or / m i crocontroller su ppl i e s only the i n i - t ia l a ddre ss , a ll subs e qu ent a ddre ss e s a re au tom a t i - c a lly gener a ted b y the dev i ce w i th a t i m i ng def i ned b y the conf i g u r a t i on reg is ter def i n i t i on . the b u r s t re a d cycle con sis t s of a n a ddre ss ph as e a nd a corre s pond- i ng d a t a ph as e . d u r i ng the a ddre ss ph as e, the addre ss v a l i d (adv#) p i n is ass erted (t a ken low) for one clock per i od . to - gether w i th the edge of the clk, the s t a rt i ng bu r s t a d- dre ss is lo a ded i nto the i ntern a l b u r s t addre ss co u nter . the i ntern a l b u r s t addre ss co u nter c a n b e conf i g u red to e i ther the l i ne a r mode s ( s ee ?in i t ia l ac- ce ss del a y conf i g u r a t i on?) . d u r i ng the d a t a ph as e, the f i r s t bu r s t d a t a is a v ai l ab le a fter the i n i t ia l a cce ss t i me del a y def i ned i n the conf i g- u r a t i on reg is ter . for subs e qu ent bu r s t d a t a , every r is - i ng (or f a ll i ng) edge of the clk w i ll tr i gger the o u tp u t d a t a w i th the bu r s t o u tp u t del a y a nd s e qu ence def i ned i n the conf i g u r a t i on reg is ter . t ab le s 17?20 s how a ll the comm a nd s exec u ted b y the dev i ce . the dev i ce au tom a t i c a lly power s u p i n the re a d/re s et s t a te . it is not nece ssa ry to issu e a re a d/re- s et comm a nd a fter power- u p or h a rdw a re re s et . read/re s et command after power- u p or h a rdw a re re s et, the am2 9 bdd160 au tom a t i c a lly enter the re a d s t a te . it is not nece ssa ry to issu e the re s et comm a nd a fter power- u p or h a rd- w a re re s et . s t a nd a rd m i croproce ss or cycle s retr i eve a rr a y d a t a , however, a fter power- u p, only as ynchro- no us a cce ss e s a re perm i tted si nce the conf i g u r a t i on reg is ter is a t i t s re s et s t a te w i th bu r s t a cce ss e s d is - ab led . the re s et comm a nd is exec u ted when the us er need s to ex i t a ny of the other us er comm a nd s e qu ence s ( su ch as au to s elect, progr a m, ch i p er as e, etc . ) to re- t u rn to re a d i ng a rr a y d a t a. there is no l a tency b e- tween exec u t i ng the re s et comm a nd a nd re a d i ng a rr a y d a t a.
june 7, 2006 am29bdd160g 35 the re s et comm a nd doe s not d isab le the s ec si s ec- tor i f i t is en ab led . th is f u nct i on is only a ccompl is hed b y issui ng the s ec si s ector ex i t comm a nd . auto s elect command fl as h memor i e s a re i ntended for us e i n a ppl i c a t i on s where the loc a l cpu a lter s memory content s. a s su ch, m a n u f a ct u rer a nd dev i ce code s m us t b e a cce ssib le wh i le the dev i ce re si de s i n the t a rget s y s tem . prom progr a mmer s typ i c a lly a cce ss the si gn a t u re code s b y r aisi ng a 9 to v id . however, m u lt i plex i ng h i gh volt a ge onto the a ddre ss l i ne s is not gener a lly de si red s y s tem de si gn pr a ct i ce . the am2 9 bdd160 cont ai n s a n a u to s elect comm a nd oper a t i on to su pplement tr a d i t i on a l prom progr a m- m i ng methodology . the oper a t i on is i n i t ia ted b y wr i t i ng the a u to s elect comm a nd s e qu ence i nto the comm a nd reg is ter . the ba nk a ddre ss (ba) is l a tched d u r i ng the au to s elect comm a nd s e qu ence wr i te oper a t i on to d is - t i ng uis h wh i ch ba nk the a u to s elect comm a nd refer- ence s. re a d i ng the other ba nk a fter the a u to s elect comm a nd is wr i tten re su lt s i n re a d i ng a rr a y d a t a from the other ba nk a nd the s pec i f i ed a ddre ss. follow i ng the comm a nd wr i te, a re a d cycle from a ddre ss (ba)xx00h retr i eve s the m a n u f a ct u rer code of (ba)xx01h . three s e qu ent ia l re a d cycle s a t a d- dre ss e s (ba) xx01h, (ba) xx0eh, a nd (ba) xx0fh re a d the three- b yte dev i ce id ( s ee t ab le s 1 9 a nd 20) . all m a n u f a ct u rer a nd dev i ce code s exh ibi t odd p a r i ty w i th the m s b of the lower b yte (dq7) def i ned as the p a r i ty bi t . (the a u to s elect comm a nd re qui re s the us er to exe- c u te the re a d/re s et comm a nd to ret u rn the dev i ce ba ck to re a d i ng the a rr a y content s. ) pro g ram command s equence progr a mm i ng is a fo u r- bus -cycle oper a t i on . the pro- gr a m comm a nd s e qu ence is i n i t ia ted b y wr i t i ng two u nlock wr i te cycle s , followed b y the progr a m s et- u p comm a nd . the progr a m a ddre ss a nd d a t a a re wr i tten next, wh i ch i n t u rn i n i t ia te the em b edded progr a m a l- gor i thm . the s y s tem is not re qui red to prov i de f u rther control s or t i m i ng s. the dev i ce au tom a t i c a lly gener- a te s the progr a m p u l s e s a nd ver i f i e s the progr a mmed cell m a rg i n . t ab le s 1 8 a nd 20 s how s the a ddre ss a nd d a t a re qui rement s for the progr a m comm a nd s e- qu ence . d u r i ng the em b edded progr a m a lgor i thm, the s y s tem c a n determ i ne the s t a t us of the progr a m oper a t i on b y usi ng dq7, dq6, or ry/by# . ( s ee wr i te oper a t i on s t a t us for i nform a t i on on the s e s t a t us bi t s. ) when the em b edded progr a m a lgor i thm is complete, the dev i ce ret u rn s to re a d i ng a rr a y d a t a a nd a ddre ss e s a re no longer l a tched . note th a t a n a ddre ss ch a nge is re- qui red to b eg i n re a d v a l i d a rr a y d a t a. except for progr a m sus pend, a ny comm a nd s wr i tten to the dev i ce d u r i ng the em b edded progr a m algor i thm a re i gnored . note th a t a hardware re s et i mmed ia tely term i n a te s the progr a mm i ng oper a t i on . the comm a nd s e qu ence s ho u ld b e re i n i t ia ted once th a t ba nk h as re- t u rned to re a d i ng a rr a y d a t a , to en su re d a t a i ntegr i ty . progr a mm i ng is a llowed i n a ny s e qu ence a nd a cro ss s ector b o u nd a r i e s. a b i t cannot be pro g rammed from a ?0? back to a ?1? . attempt i ng to do s o m a y h a lt the oper a t i on a nd s et dq5 to ?1,? or c aus e the d a t a # poll i ng a lgor i thm to i nd i c a te the oper a t i on w as su cce ss f u l . however, a su cceed i ng re a d w i ll s how th a t the d a t a is s t i ll ?0? . only er as e oper a t i on s c a n convert a ?0? to a ?1? . accelerated pro g ram command the acceler a ted ch i p progr a m mode is de si gned to i mprove the word or do ub le word progr a mm i ng s peed . improv i ng the progr a mm i ng s peed is a ccom- pl is hed b y usi ng the acc p i n to su pply b oth the word- l i ne volt a ge a nd the bi tl i ne c u rrent i n s te a d of usi ng the v pp p u mp a nd dr ai n p u mp, wh i ch is l i m i ted to 2 . 5 ma . bec aus e the extern a l acc p i n is c a p ab le of su pply i ng si gn i f i c a ntly l a rge a mo u nt s of c u rrent comp a red to the dr ai n p u mp, a ll 3 2 bi t s a re a v ai l ab le for progr a mm i ng w i th a si ngle progr a mm i ng p u l s e . th is is a n enormo us i mprovement over the s t a nd a rd 5- bi t progr a mm i ng . if the us er is ab le to su pply a n extern a l power su pply a nd connect i t to the acc p i n, si gn i f i c a nt t i me sa v i ng s a re re a l i zed . in order to enter the acceler a ted progr a m mode, the acc p i n m us t f i r s t b e t a ken to v hh (12 v 0 . 5 v) a nd followed b y the one-cycle comm a nd w i th the progr a m a ddre ss a nd d a t a to follow . the acceler a ted ch i p pro- gr a m comm a nd is only exec u ted when the dev i ce is i n unlock byp ass mode a nd d u r i ng norm a l re a d/re s et oper a t i ng mode . in th is mode, the wr i te protect i on f u nct i on is b yp ass ed u nle ss the ppb lock b i t = 1 . the acceler a ted progr a m comm a nd is not perm i tted i f the s ec si s ector is en ab led . unlock bypa ss command s equence the u nlock b yp ass fe a t u re a llow s the s y s tem to pro- gr a m word s to the dev i ce f as ter th a n usi ng the s t a n- d a rd progr a m comm a nd s e qu ence . the u nlock b yp ass comm a nd s e qu ence is i n i t ia ted b y f i r s t wr i t i ng two u n- lock cycle s. th is is followed b y a th i rd wr i te cycle con- t ai n i ng the u nlock b yp ass comm a nd, 20h . the dev i ce then enter s the u nlock b yp ass mode . a two-cycle u n- lock b yp ass progr a m comm a nd s e qu ence is a ll th a t is re qui red to progr a m i n th is mode . the f i r s t cycle i n th is s e qu ence cont ai n s the u nlock b yp ass progr a m com- m a nd, a0h ; the s econd cycle cont ai n s the progr a m a ddre ss a nd d a t a. add i t i on a l d a t a is progr a mmed i n
36 am29bdd160g june 7, 2006 the sa me m a nner . th is mode d is pen s e s w i th the i n i t ia l two u nlock cycle s re qui red i n the s t a nd a rd progr a m comm a nd s e qu ence, re su lt i ng i n f as ter tot a l progr a m- m i ng t i me . t ab le s 1 8 a nd 20 s how the re qui rement s for the comm a nd s e qu ence . d u r i ng the u nlock b yp ass mode, only the unlock by- p ass progr a m a nd unlock byp ass re s et comm a nd s a re v a l i d . to e x i t the u nlock b yp ass mode, the s y s tem m us t issu e the two-cycle u nlock b yp ass re s et com- m a nd s e qu ence . the f i r s t cycle m us t cont ai n the d a t a 9 0h ; the s econd cycle the d a t a 00h . addre ss e s a re don?t c a re for b oth cycle s. the dev i ce then ret u rn s to re a d i ng a rr a y d a t a. f i g u re 5 i ll us tr a te s the a lgor i thm for the progr a m oper- a t i on . s ee the er as e/progr a m oper a t i on s t ab le i n ac ch a r a cter is t i c s for p a r a meter s , a nd to f i g u re 22 for t i m i ng d ia gr a m s. unlock bypa ss entry command the unlock byp ass comm a nd, once issu ed, is us ed to b yp ass the ? u nlock? s e qu ence for progr a m, ch i p er as e, a nd cfi comm a nd s. th is fe a t u re perm i t s s low prom progr a mmer s to si gn i f i c a ntly i mprove progr a m- m i ng/er as e thro u ghp u t si nce the comm a nd s e qu ence often re qui re s m i cro s econd s to exec u te a si ngle wr i te oper a t i on . therefore, once the unlock byp ass com- m a nd is issu ed, only the two-cycle progr a m a nd er as e b yp ass comm a nd s a re re qui red . the unlock byp ass comm a nd is i gnored i f the s ec si s ector is en ab led . to ret u rn ba ck to norm a l oper a t i on, the unlock byp ass re s et comm a nd m us t b e issu ed . the follow i ng fo u r s ect i on s de s cr ib e the comm a nd s th a t m a y b e exec u ted w i th i n the u nlock b yp ass mode . unlock bypa ss pro g ram command the unlock byp ass progr a m comm a nd is a two-cycle comm a nd th a t con sis t s of the a ct ua l progr a m com- m a nd (a0h) a nd the progr a m a ddre ss /d a t a com bi n a - t i on . th is comm a nd doe s not re qui re the two-cycle ? u nlock? s e qu ence si nce the unlock byp ass comm a nd w as prev i o us ly issu ed . a s w i th the s t a nd a rd progr a m comm a nd, m u lt i ple unlock byp ass progr a m com- m a nd s c a n b e issu ed once the unlock byp ass com- m a nd is issu ed . to re t u rn ba ck to s t a nd a rd re a d oper a t i on s , the unlock byp ass re s et comm a nd m us t b e issu ed . the unlock byp ass progr a m comm a nd is i gnored i f the s ec si s ector is en ab led . unlock bypa ss ch i p era s e command the unlock byp ass ch i p er as e comm a nd is a 2-cycle comm a nd th a t con sis t s of the er as e s et u p comm a nd ( 8 0h) a nd the a ct ua l ch i p er as e comm a nd (10h) . th is comm a nd doe s not re qui re the two-cycle ? u nlock? s e- qu ence si nce the unlock byp ass comm a nd w as prev i - o us ly issu ed . unl i ke the s t a nd a rd er as e comm a nd, there is no unlock byp ass er as e sus pend or er as e re su me comm a nd s. to re t u rn ba ck to s t a nd a rd re a d oper a t i on s , the unlock byp ass re s et comm a nd m us t b e issu ed . the unlock byp ass progr a m comm a nd is i gnored i f the s ec si s ector is en ab led . unlock bypa ss cfi command the unlock byp ass cfi comm a nd is a v ai l ab le for prom progr a mmer s a nd t a rget s y s tem s to re a d the cfi code s wh i le i n unlock byp ass mode . s ee com- mon fl as h memory interf a ce (cfi) for s pec i f i c cfi code s. to re t u rn ba ck to s t a nd a rd re a d oper a t i on s , the unlock byp ass re s et comm a nd m us t b e issu ed . the unlock byp ass progr a m comm a nd is i gnored i f the s ec si s ector is en ab led . s tart wr i te progr a m comm a nd s e qu ence d a t a poll from s y s tem ver i fy d a t a ? no ye s l as t addre ss ? no ye s progr a mm i ng completed increment addre ss em b edded progr a m a lgor i thm i n progre ss note: see t ab le s 18 a nd 20 for progr a m comm a nd s e- qu ence . f ig ure 4 . pro g ram operat i on
june 7, 2006 am29bdd160g 37 unlock bypa ss re s et command the unlock byp ass re s et comm a nd pl a ce s the dev i ce i n s t a nd a rd re a d/re s et oper a t i ng mode . once exe- c u ted, norm a l re a d oper a t i on s a nd us er comm a nd s e- qu ence s a re a v ai l ab le for exec u t i on . the unlock byp ass progr a m comm a nd is i gnored i f the s ec si s ector is en ab led . ch i p era s e command the ch i p er as e comm a nd is us ed to er as e the ent i re fl as h memory content s of the ch i p b y issui ng a si ngle comm a nd . ch i p er as e is a si x- bus cycle oper a t i on . there a re two ? u nlock? wr i te cycle s , followed b y wr i t i ng the er as e ? s et u p? comm a nd . two more ? u nlock? wr i te cycle s a re followed b y the ch i p er as e comm a nd . ch i p er as e doe s not er as e protected s ector s. the ch i p er as e oper a t i on i n i t ia te s the em b edded er as e a lgor i thm, wh i ch au tom a t i c a lly preprogr a m s a nd ver i f i e s the ent i re memory to a n a ll zero p a ttern pr i or to electr i c a l er as e . the s y s tem is not re qui red to pro- v i de a ny control s or t i m i ng s d u r i ng the s e oper a t i on s. note th a t a hardware re s et i mmed ia tely term i n a te s the progr a mm i ng oper a t i on . the comm a nd s e qu ence s ho u ld b e re i n i t ia ted once th a t ba nk h as ret u rned to re a d i ng a rr a y d a t a , to en su re d a t a i ntegr i ty . the em b edded er as e a lgor i thm er as e b eg i n s on the r isi ng edge of the l as t we# or ce# p u l s e (wh i chever occ u r s f i r s t) i n the comm a nd s e qu ence . the s t a t us of the er as e oper a t i on is determ i ned three w a y s: d a t a # poll i ng of the dq7 p i n ( s ee dq7 : d a t a # poll- i ng ) check i ng the s t a t us of the toggle bi t dq6 ( s ee dq6 : toggle b i t i ) check i ng the s t a t us of the ry/by# p i n ( s ee ry/by# : re a dy/b us y# ) once er asu re h as b eg u n, only the er as e sus pend comm a nd is v a l i d . all other comm a nd s a re i gnored . when the em b edded er as e a lgor i thm is complete, the dev i ce ret u rn s to re a d i ng a rr a y d a t a , a nd a ddre ss e s a re no longer l a tched . note th a t a n a ddre ss ch a nge is re qui red to b eg i n re a d v a l i d a rr a y d a t a. f i g u re 5 i ll us tr a te s the em b edded er as e algor i thm . s ee the er as e/progr a m oper a t i on s t ab le s i n ac ch a r- a cter is t i c s for p a r a meter s , a nd to f i g u re 22 for t i m i ng d ia gr a m s. s ector era s e command the s ector er as e comm a nd is us ed to er as e i nd i v i d- ua l s ector s or the ent i re fl as h memory content s. s ec- tor er as e is a si x- bus cycle oper a t i on . there a re two ? u nlock? wr i te cycle s , followed b y wr i t i ng the er as e ? s et u p? comm a nd . two more ? u nlock? wr i te cycle s a re then followed b y the er as e comm a nd ( 3 0h) . the s ec- tor a ddre ss ( a ny a ddre ss loc a t i on w i th i n the de si red s ector) is l a tched on the f a ll i ng edge of we# or ce# (wh i chever occ u r s l as t) wh i le the comm a nd ( 3 0h) is l a tched on the r isi ng edge of we# or ce# (wh i chever occ u r s f i r s t) . s pec i fy i ng m u lt i ple s ector s for er as e is a ccompl is hed b y wr i t i ng the si x bus cycle oper a t i on, as de s cr ib ed ab ove, a nd then follow i ng i t b y a dd i t i on a l wr i te s of only the l as t cycle of the s ector er as e comm a nd to a d- dre ss e s or other s ector s to b e er as ed . the t i me b e- tween s ector er as e comm a nd wr i te s m us t b e le ss th a n 8 0 s , otherw is e the comm a nd is re j ected . it is recommended th a t proce ss or i nterr u pt s b e d isab led d u r i ng th is t i me to g ua r a ntee th is cr i t i c a l t i m i ng cond i - t i on . the i nterr u pt s c a n b e re-en ab led a fter the l as t s ector er as e comm a nd is wr i tten . a t i me-o u t of 8 0 s from the r isi ng edge of the l as t we# (or ce#) w i ll i n i - t ia te the exec u t i on of the s ector er as e comm a nd( s ) . if a nother f a ll i ng edge of the we# (or ce#) occ u r s w i th i n the 8 0 s t i me-o u t w i ndow, the t i mer is re s et . once the 8 0 s w i ndow h as t i med o u t a nd er asu re h as b eg u n, only the er as e sus pend comm a nd is recogn i zed ( s ee s ector er as e a nd progr a m sus pend comm a nd a nd s ector er as e a nd progr a m re su me comm a nd s ec- t i on s ) . if th a t occ u r s , the s ector er as e comm a nd s e- qu ence s ho u ld b e re i n i t ia ted once th a t ba nk h as ret u rned to re a d i ng a rr a y d a t a , to en su re d a t a i ntegr i ty . lo a d i ng the s ector er as e reg is ter s m a y b e done i n a ny s e qu ence a nd w i th a ny n u m b er of s ector s. s ector er as e doe s not re qui re the us er to progr a m the dev i ce pr i or to er as e . the dev i ce au tom a t i c a lly prepro- gr a m s a ll memory loc a t i on s , w i th i n s ector s to b e er as ed, pr i or to electr i c a l er as e . when er asi ng a s ec- tor or s ector s , the rem ai n i ng u n s elected s ector s or the wr i te protected s ector s a re u n a ffected . the s y s tem is not re qui red to prov i de a ny control s or t i m i ng s d u r i ng s ector er as e oper a t i on s. the er as e sus pend a nd er as e re su me comm a nd s m a y b e wr i tten as often as re qui red d u r i ng a s ector er as e oper a t i on . a u tom a t i c s ector er as e oper a t i on s b eg i n on the r isi ng edge of the we# or ce# p u l s e of the l as t s ector er as e comm a nd issu ed, a nd once the 8 0 s t i me-o u t w i ndow h as exp i red . the s t a t us of the s ector er as e oper a t i on is determ i ned three w a y s: d a t a # poll i ng of the dq7 p i n check i ng the s t a t us of the toggle bi t dq6 check i ng the s t a t us of the ry/by# p i n f u rther s t a t us of dev i ce a ct i v i ty d u r i ng the s ector er as e oper a t i on is determ i ned usi ng toggle bi t dq2 (refer to dq2 : toggle b i t ii ) . when the em b edded er as e a lgor i thm is complete, the dev i ce ret u rn s to re a d i ng a rr a y d a t a , a nd a ddre ss e s a re no longer l a tched . note th a t a n a ddre ss ch a nge is re qui red to b eg i n re a d v a l i d a rr a y d a t a.
38 am29bdd160g june 7, 2006 f i g u re 5 i ll us tr a te s the em b edded? er as e algor i thm, usi ng a typ i c a l comm a nd s e qu ence a nd bus oper a t i on . refer to the er as e/progr a m oper a t i on s t ab le s i n the ac ch a r a cter is t i c s s ect i on for p a r a meter s , a nd to f i g- u re 22 for t i m i ng d ia gr a m s. s ector era s e and pro g ram s u s pend command the s ector er as e a nd progr a m sus pend comm a nd a l- low s the us er to i nterr u pt a s ector er as e or progr a m oper a t i on a nd perform d a t a re a d or progr a m s i n a s ec- tor th a t is not b e i ng er as ed or to the s ector where a progr a mm i ng oper a t i on w as i n i t ia ted . th is comm a nd is a ppl i c ab le only d u r i ng the s ector er as e a nd pro- gr a mm i ng oper a t i on, wh i ch i ncl u de s the t i me-o u t pe- r i od for s ector er as e . s ector era s e and pro g ram s u s pend operat i on mechan i c s a su cce ss f u l er as e p u l s e h as a d u r a t i on or 1 . 2 m s 20 % , depend i ng on the n u m b er of prev i o us er as e cycle s ( a mong other f a ctor s ) . a su cce ss f u l s ector er as e oper a t i on re qui re s 3 00 su cce ss f u l er as e p u l s e s. an i ntern a l co u nter mon i tor s the n u m b er of er as e p u l s e s i n i t ia ted a nd h as a m a x i m u m v a l u e of 5 98 0 . the co u nter is i ncremented b y one every t i me a n er as e p u l s e is i n i t ia ted, reg a rdle ss of whether or not th a t er as e p u l s e is su cce ss f u l . an er as e p u l s e is ter- m i n a ted i mmed ia tely when the sus pend comm a nd is exec u ted . a new er as e p u l s e is i n i t ia ted when the re su me comm a nd is exec u ted ( a nd the co u nter is i ncremented) . g i ven th a t 3 00 su cce ss f u l er as e p u l s e s a re re- qui red, a su cce ss f u l s ector er as e oper a t i on s h a ll h a ve a m a x i m u m of 56 8 0 er as e sus pend s. the s ector er as e a nd progr a m sus pend comm a nd is i gnored i f wr i tten d u r i ng the exec u t i on of the ch i p er as e oper a t i on or em b edded progr a m algor i thm ( bu t w i ll re s et the ch i p i f wr i tten i mproperly d u r i ng the com- m a nd s e qu ence s ) . wr i t i ng the s ector er as e a nd pro- gr a m comm a nd d u r i ng the s ector er as e t i me-o u t re su lt s i n i mmed ia te term i n a t i on of the t i me-o u t per i od a nd sus pen si on of the er as e oper a t i on . once i n er as e sus pend, the dev i ce is a v ai l ab le for re a d i ng (note th a t i n the er as e sus pend mode, the re s et comm a nd is not re qui red for re a d oper a t i on s a nd is i gnored) or pro- gr a m oper a t i on s i n s ector s not b e i ng er as ed . any other comm a nd wr i tten d u r i ng the er as e sus pend mode is i gnored, except for the s ector er as e a nd pro- gr a m re su me comm a nd . wr i t i ng the er as e a nd pro- gr a m re su me comm a nd re su me s the s ector er as e oper a t i on . the ba nk a ddre ss of the er as e sus pended ba nk is re qui red when wr i t i ng th is comm a nd if the s ector er as e a nd progr a m sus pend comm a nd is wr i tten d u r i ng a progr a mm i ng oper a t i on, the dev i ce sus pend s progr a mm i ng oper a t i on s a nd a llow s only re a d oper a t i on s i n s ector s not s elected for progr a m- m i ng . f u rther ne s t i ng of e i ther er as e or progr a mm i ng oper a t i on s is not perm i tted . t ab le 1 8 su mm a r i ze s per- m issib le oper a t i on s d u r i ng er as e a nd progr a m sus - pend . (a bus y s ector is one th a t is s elected for progr a mm i ng or er asu re . ) : table 1 8. allowed operat i on s dur i n g era s e/pro g ram s u s pend when the s ector er as e a nd progr a m sus pend com- m a nd is wr i tten d u r i ng a s ector er as e oper a t i on, the ch i p w i ll t a ke b etween 0 . 1 s a nd 20 s to a ct ua lly sus pend the oper a t i on a nd go i nto the er as e sus - pended re a d mode (p s e u do-re a d mode), a t wh i ch t i me the us er c a n re a d or progr a m from a s ector th a t is not er as e sus pended . re a d i ng d a t a i n th is mode is the sa me as re a d i ng from the s t a nd a rd re a d mode, except th a t the d a t a m us t b e re a d from s ector s th a t h a ve not b een er as e sus pended . poll i ng dq6 on two i mmed ia tely con s ec u t i ve re a d s from a g i ven a ddre ss prov i de s the s y s tem w i th the s tart wr i te er as e comm a nd s e qu ence d a t a poll from s y s tem d a t a = ffh? no ye s er asu re completed em b edded er as e a lgor i thm i n progre ss notes: 1 . see t ab le s 18 a nd 20 for er as e comm a nd s e qu ence . 2 . see dq3 : sector er as e t i mer for more i nform a t i on . f ig ure 5 . era s e operat i on s ector pro g ram s u s pend era s e s u s pend b us y s ector progr a m re su me er as e re su me non- bus y s ector s re a d only re a d or progr a m
june 7, 2006 am29bdd160g 39 abi l i ty to determ i ne i f the dev i ce is i n er as e or progr a m sus pend . before the dev i ce enter s er as e or progr a m sus pend, the dq6 p i n toggle s b etween two i mmed i - a tely con s ec u t i ve re a d s from the sa me a ddre ss. after the dev i ce h as entered er as e sus pend, dq6 s top s toggl i ng b etween two i mmed ia tely con s ec u t i ve re a d s to the sa me a ddre ss. d u r i ng the s ector er as e oper a - t i on a nd a l s o i n er as e sus pend mode, two i mmed ia tely con s ec u t i ve re a d i ng s from the er as e- sus pended s ec- tor c aus e s dq2 to toggle . dq2 doe s not toggle i f re a d- i ng from a non- bus y (non-er asi ng) s ector ( s tored d a t a is re a d) . no bi t s a re toggled d u r i ng progr a m sus pend mode . s oftw a re m us t keep tr a ck of the f a ct th a t the dev i ce is i n a sus pended mode . after enter i ng the er as e- sus pend-re a d mode, the s y s - tem m a y re a d or progr a m w i th i n a ny non- sus pended s ector : a re a d oper a t i on from the er as e- sus pended ba nk ret u rn s poll i ng d a t a d u r i ng the f i r s t 8 s a fter the er as e sus pend comm a nd is issu ed ; re a d oper a t i on s there a fter ret u rn a rr a y d a t a. re a d oper a t i on s from the other ba nk ret u rn a rr a y d a t a w i th no l a tency . a progr a m oper a t i on wh i le i n the er as e sus pend mode is the sa me as progr a mm i ng i n the reg u l a r progr a m mode, except th a t the d a t a m us t b e pro- gr a mmed to a s ector th a t is not er as e sus pended . wr i te oper a t i on s t a t us is o b t ai ned i n the sa me m a n- ner as a norm a l progr a m oper a t i on . s ector era s e and pro g ram re s ume command the s ector er as e a nd progr a m re su me comm a nd ( 3 0h) re su me s a s ector er as e or progr a m oper a t i on th a t h as b een sus pended . any f u rther wr i te s of the s ector er as e a nd progr a m re su me comm a nd i g- nored . however, a nother s ector er as e a nd progr a m sus pend comm a nd c a n b e wr i tten a fter the dev i ce h as re su med s ector er as e oper a t i on s. note th a t u nt i l a sus pended progr a m or er as e oper a t i on h as re su med, the content s of th a t s ector a re u nknown . the s ector er as e a nd progr a m re su me comm a nd is i gnored i f the s ec si s ector is en ab led . conf ig urat i on re gis ter read command the conf i g u r a t i on reg is ter re a d comm a nd is us ed to ver i fy the content s of the conf i g u r a t i on reg is ter . exe- c u t i on of th is comm a nd is only a llowed wh i le i n us er mode a nd is not a v ai l ab le d u r i ng unlock byp ass mode or d u r i ng s ec u r i ty mode . the conf i g u r a t i on reg is ter re a d comm a nd is preceded b y the s t a nd a rd two-cycle ? u nlock? s e qu ence, followed b y the conf i g u r a t i on reg- is ter re a d comm a nd (c6h), a nd f i n a lly followed b y perform i ng a re a d oper a t i on to the ba nk a ddre ss s pec- i f i ed when the c6h comm a nd w as wr i tten . re a d i ng the other ba nk re su lt s i n re a d i ng the fl as h memory con- tent s. the content s of the conf i g u r a t i on reg is ter a re pl a ce on dq15?dq0 . if word# is a t v ih ( 3 2- bi t dq b us ), the content s of dq 3 1?dq16 a re xxxxh a nd s ho u ld b e i gnored . the us er s ho u ld exec u te the re a d/re s et comm a nd to pl a ce the dev i ce ba ck i n s t a nd a rd us er oper a t i on a fter exec u t i ng the conf i g u r a - t i on reg is ter re a d comm a nd . the conf i g u r a t i on reg is ter re a d comm a nd is f u lly oper a t i on a l i f the s ec si s ector is en ab led . conf ig urat i on re gis ter wr i te command the conf i g u r a t i on reg is ter wr i te comm a nd is us ed to mod i fy the content s of the conf i g u r a t i on reg is ter . ex- ec u t i on of th is comm a nd is only a llowed wh i le i n us er mode a nd is not a v ai l ab le d u r i ng unlock byp ass mode or d u r i ng s ec u r i ty mode . the conf i g u r a t i on reg is ter wr i te comm a nd is preceded b y the s t a nd a rd two-cycle ? u nlock? s e qu ence, followed b y the conf i g u r a t i on reg- is ter wr i te comm a nd (d0h), a nd f i n a lly followed b y wr i t i ng the content s of the conf i g u r a t i on reg is ter to a ny a ddre ss. the content s of the conf i g u r a t i on reg is - ter a re pl a ce on dq15?dq0 . if word# is a t v ih ( 3 2- bi t dq b us ), the content s of dq 3 1?dq16 a re xxxxh a nd a re i gnored . wr i t i ng the conf i g u r a t i on reg is ter wh i le a n em b edded algor i thm? or er as e sus pend mode s a re exec u t i ng re su lt s i n the content s of the conf i g u r a t i on reg is ter not b e i ng u pd a ted . the conf i g u r a t i on reg is ter re a d comm a nd is f u lly oper a t i on a l i f the s ec si s ector is en ab led . common fla s h interface (cfi) command the common fl as h interf a ce (cfi) comm a nd pro- v i de s dev i ce si ze, geometry, a nd c a p abi l i ty i nform a t i on d i rectly to the us er s s y s tem . fl as h dev i ce s th a t su p- port cfi, h a ve a ?q u ery comm a nd? th a t ret u rn s i nfor- m a t i on ab o u t the dev i ce to the s y s tem . the q u ery s tr u ct u re content s a re re a d a t the s pec i f i c a ddre ss lo- c a t i on s follow i ng a si ngle s y s tem wr i te cycle where : a 98 h qu ery comm a nd code is wr i tten to 55h a d- dre ss loc a t i on w i th i n the dev i ce? s a ddre ss s p a ce the dev i ce is i n i t ia lly i n a ny v a l i d re a d s t a te, su ch as ?re a d arr a y? or ?re a d id d a t a ? other dev i ce s t a t is t i c s m a y ex is t w i th i n a long s e- qu ence of comm a nd s or d a t a i np u t ; su ch s e qu ence s m us t f i r s t b e completed or term i n a ted b efore wr i t i ng of the 98 h q u ery comm a nd, otherw is e i nv a l i d q u ery d a t a s tr u ct u re o u tp u t m a y re su lt . note th a t for d a t a bus bi t s gre a ter th a n dq7 (dq 3 1?dq 8 ), the v a l i d q u ery a cce ss code h as a ll ze- roe s (?0? s ) i n the u pper dq bus loc a t i on s. th us , the 16- bi t q u ery comm a nd code is 00 98 h a nd the 3 2- bi t q u ery comm a nd code is 000000 98 h . to t e r m i n a te the cfi oper a t i on, i t is nece ssa ry to exe- c u te the re a d/re s et comm a nd .
40 am29bdd160g june 7, 2006 the cfi comm a nd is not perm i tted i f the s ec si s ector is en ab led a nd si m u lt a neo us oper a t i on is d isab led once the comm a nd is entered . s ee common fl as h memory interf a ce (cfi) for the s pec i f i c cfi comm a nd code s.
june 7, 2006 am29bdd160g 41 s ec si s ector entry command the s ec si s ector entry comm a nd en ab le s the s ec si (otp) s ector to overl a y the 8 kb o u termo s t s ector i n the s m a ll (25 % ) ba nk . the s ec si s ector overl a y s 00000h?000 3 fh for the top b oot b lock conf i g u r a t i on a nd 7ffc0h?7ffffh for the b ottom b oot b lock conf iu - r a t i on . addre ss r a nge 00040h?007ffh for the top b oot b lock a nd 7f 8 00h?7ffbfh ret u rn i nv a l i d d a t a when a ddre ss ed w i th the s ec si s ector en ab led . the follow i ng comm a nd s a re perm i tted a fter issui ng the s ec si s ector entry comm a nd : 1 . a u to s elect 2 . p ass word progr a m (x16 a nd x 3 2) 3. p ass word ver i fy 4 . p ass word unlock (x16 a nd x 3 2) 5 . re a d/re s et 6 . progr a m 7 . ch i p a nd s ector er as e 8. s ec si s ector protect i on b i t progr a m 9. ppb progr a m 10 . all ppb er as e 11 . ppb lock b i t s et 12 . dyb wr i te 1 3. dyb/ppb/ppb lock b i t ver i fy 14 .s ec u r i ty re s et 15 . conf i g u r a t i on reg is ter wr i te 16 . conf i g u r a t i on reg is ter re a d the follow i ng comm a nd s a re u n a v ai l ab le when the s ec si s ector is en ab led . i ssui ng the follow i ng com- m a nd s wh i le the s ec si s ector is en ab led re su lt s i n the comm a nd b e i ng i gnored . 1 . unlock byp ass 2 . cfi 3. acceler a ted progr a m 4 . progr a m a nd s ector er as e sus pend 5 . progr a m a nd s ector er as e re su me the s ec si s ector entry comm a nd is a llowed when the dev i ce is i n e i ther progr a m or er as e sus pend mode s. if the s ec si s ector is en ab led, the progr a m or er as e sus - pend comm a nd is i gnored . th is prevent s re su m i ng e i - ther progr a mm i ng or er asu re on the s ec si s ector i f the overl a yed s ector w as u ndergo i ng progr a mm i ng or er a - su re . the ho s t s y s tem mu s t en s ure that the dev i ce re s ume any s u s pended pro g ram or era s e opera- t i on after ex i t i n g the s ec si s ector . exec u t i ng a ny of the ppb progr a m/er as e comm a nd s , or p ass word unlock comm a nd re su lt s i n the s m a ll ba nk (25 % ba nk) ret u rn i ng the s t a t us of the s e oper a - t i on s wh i le they a re i n progre ss , th us m a k i ng the s ec si s ector u n a v ai l ab le for re a d i ng . if the s ec si s ec- tor is en ab led wh i le the dyb comm a nd is issu ed, the dyb for the overl a yed s ector is not u pd a ted . re a d- i ng the dyb s t a t us usi ng the ppb lock b i t/dybdyb ver i fy comm a nd when the s ec si s ector is en ab led re- t u rn s i nv a l i d d a t a. pa ss word pro g ram command the p ass word progr a m comm a nd perm i t s progr a m- m i ng the p ass word th a t is us ed as p a rt of the h a rd- w a re protect i on s cheme . the a ct ua l p ass word is 64- bi t s long . depend i ng u pon the s t a te of the word# p i n, m u lt i ple p ass word progr a m comm a nd s a re re- qui red . for a x16 bi t d a t a bus , 4 p ass word progr a m comm a nd s a re re qui red to progr a m the p ass word . for a x 3 2 bi t d a t a bus , 2 p ass word progr a m comm a nd s a re re qui red . the us er m us t enter the u nlock cycle, p ass word progr a m comm a nd ( 38 h) a nd the progr a m a ddre ss /d a t a for e a ch port i on of the p ass word when progr a mm i ng . there a re no prov isi on s for enter i ng the 2-cycle u nlock cycle, the p ass word progr a m com- m a nd, a nd a ll the p ass word d a t a. there is no s pec ia l a ddre ssi ng order re qui red for progr a mm i ng the p ass - word . al s o, when the p ass word is u ndergo i ng pro- gr a mm i ng, si m u lt a neo us oper a t i on is d isab led . re a d oper a t i on s to a ny memory loc a t i on w i ll ret u rn the pro- gr a mm i ng s t a t us. once progr a mm i ng is complete, the us er m us t issu e a re a d/re s et comm a nd to ret u rn the dev i ce to norm a l oper a t i on . once the p ass word is wr i tten a nd ver i f i ed, the p ass word mode lock i ng b i t m us t b e s et i n order to prevent ver i f i c a t i on . the p ass - word progr a m comm a nd is only c a p ab le of progr a m- m i ng ?0? s. progr a mm i ng a ?1? a fter a cell is progr a mmed as a ?0? re su lt s i n a t i me-o u t b y the em- b edded progr a m algor i thm? w i th the cell rem ai n i ng as a ?0? . the p ass word is a ll f? s when s h i pped from the f a ctory . all 64- bi t p ass word com bi n a t i on s a re v a l i d as a p ass word . p ass word progr a mm i ng is perm i tted i f the s ec si s ec- tor is en ab led . pa ss word ver i fy command the p ass word ver i fy comm a nd is us ed to ver i fy the p ass word . the p ass word is ver i f iab le only when the p ass word mode lock i ng b i t is not progr a mmed . if the p ass word mode lock i ng b i t is progr a mmed a nd the us er a ttempt s to ver i fy the p ass word, the dev i ce w i ll a lw a y s dr i ve a ll f? s onto the dq d a t a bus. the p ass word ver i fy comm a nd is perm i tted i f the s ec si s ector is en ab led . al s o, the dev i ce w i ll not oper- a te i n si m u lt a neo us oper a t i on when the p ass word ver i fy comm a nd is exec u ted . only the p ass word is re- t u rned reg a rdle ss of the ba nk a ddre ss. the lower two a ddre ss bi t s (a0 : a-1) a re v a l i d d u r i ng the p ass word
42 am29bdd160g june 7, 2006 ver i fy . wr i t i ng the re a d/re s et comm a nd ret u rn s the dev i ce ba ck to norm a l oper a t i on . pa ss word protect i on mode lock i n g b i t pro g ram command the p ass word protect i on mode lock i ng b i t progr a m comm a nd progr a m s the p ass word protect i on mode lock i ng b i t, wh i ch prevent s f u rther ver i f i e s or u pd a te s to the p ass word . once progr a mmed, the p ass word protect i on mode lock i ng b i t c a nnot b e er as ed! if the p ass word protect i on mode lock i ng b i t is ver i f i ed as progr a m w i tho u t m a rg i n, the p ass word protect i on mode lock i ng b i t progr a m comm a nd c a n b e exec u ted to i mprove the progr a m m a rg i n . once the p ass word protect i on mode lock i ng b i t is progr a mmed, the per- sis tent s ector protect i on lock i ng b i t progr a m c i rc ui try is d isab led, there b y forc i ng the dev i ce to rem ai n i n the p ass word protect i on mode . ex i t i ng the mode lock i ng b i t progr a m comm a nd is a ccompl is hed b y wr i t i ng the re a d/re s et comm a nd . the p ass word protect i on mode lock i ng b i t progr a m comm a nd is perm i tted i f the s ec si s ector is en ab led . per sis tent s ector protect i on mode lock i n g b i t pro g ram command the per sis tent s ector protect i on mode lock i ng b i t progr a m comm a nd progr a m s the per sis tent s ector protect i on mode lock i ng b i t, wh i ch prevent s the p ass - word mode lock i ng b i t from ever b e i ng progr a mmed . if the per sis tent s ector protect i on mode lock i ng b i t is ver i f i ed as progr a mmed w i tho u t m a rg i n, the per sis tent s ector protect i on mode lock i ng b i t progr a m com- m a nd s ho u ld b e re issu ed to i mprove progr a m m a rg i n . by d isab l i ng the progr a m c i rc ui try of the p ass word mode lock i ng b i t, the dev i ce is forced to rem ai n i n the per sis tent s ector protect i on mode of oper a t i on, once th is bi t is s et . ex i t i ng the per sis tent protect i on mode lock i ng b i t progr a m comm a nd is a ccompl is hed b y wr i t i ng the re a d/re s et comm a nd . the per sis tent s ector protect i on mode lock i ng b i t progr a m comm a nd is perm i tted i f the s ec si s ector is en ab led . s ec si s ector protect i on b i t pro g ram command the s ec si s ector protect i on b i t progr a m comm a nd progr a m s the s ec si s ector protect i on b i t, wh i ch pre- vent s the s ec si s ector memory from b e i ng cle a red . if the s ec si s ector protect i on b i t is ver i f i ed as pro- gr a mmed w i tho u t m a rg i n, the s ec si s ector protect i on b i t progr a m comm a nd s ho u ld b e re issu ed to i mprove progr a m m a rg i n . ex i t i ng the v cc -level s ec si s ector protect i on b i t progr a m comm a nd is a ccompl is hed b y wr i t i ng the re a d/re s et comm a nd . the s ec si s ector protect i on b i t progr a m comm a nd is perm i tted i f the s ec si s ector is en ab led . ppb lock b i t s et command the ppb lock b i t s et comm a nd is us ed to s et the ppb lock bi t i f i t is cle a red e i ther a t re s et or i f the p ass word unlock comm a nd w as su cce ss f u lly exe- c u ted . there is no ppb lock b i t cle a r comm a nd . once the ppb lock b i t is s et, i t c a nnot b e cle a red u n- le ss the dev i ce is t a ken thro u gh a power-on cle a r or the p ass word unlock comm a nd is exec u ted . upon s ett i ng the ppb lock b i t, the ppb s a re l a tched i nto the dyb s. if the p ass word mode lock i ng b i t is s et, the ppb lock b i t s t a t us is reflected as s et, even a fter a power-on re s et cycle . ex i t i ng the ppb lock b i t s et comm a nd is a ccompl is hed b y wr i t i ng the re a d/re s et comm a nd . the ppb lock b i t s et comm a nd is perm i tted i f the s ec si s ector is en ab led . dyb wr i te command the dyb wr i te comm a nd is us ed to s et or cle a r a dyb for a g i ven s ector . the h i gh order a ddre ss bi t s (a1 8 ?a11) a re issu ed a t the sa me t i me as the code 01h or 00h on dq7-dq0 . all other dq d a t a bus p i n s a re i gnored d u r i ng the d a t a wr i te cycle . the dyb s a re mod i f iab le a t a ny t i me, reg a rdle ss of the s t a te of the ppb or ppb lock b i t . the dyb s a re cle a red a t power- u p or h a rdw a re re s et . ex i t i ng the dyb wr i te comm a nd is a ccompl is hed b y wr i t i ng the re a d/re s et comm a nd . the dyb wr i te comm a nd is perm i tted i f the s ec si s ector is en ab led . pa ss word unlock command the p ass word unlock comm a nd is us ed to cle a r the ppb lock b i t s o th a t the ppb s c a n b e u nlocked for mod i f i c a t i on, there b y a llow i ng the ppb s to b ecome a c- ce ssib le for mod i f i c a t i on . the ex a ct p ass word m us t b e entered i n order for the u nlock i ng f u nct i on to occ u r . th is comm a nd c a nnot b e issu ed a ny f as ter th a n 2 s a t a t i me to prevent a h a cker from r u nn i ng thro u gh the a ll 64- bi t com bi n a t i on s i n a n a ttempt to correctly m a tch a p ass word . if the comm a nd is issu ed b efore the 2 s exec u t i on w i ndow for e a ch port i on of the u nlock, the comm a nd w i ll b e i gnored . the p ass word unlock f u nct i on is a ccompl is hed b y wr i t i ng p ass word unlock comm a nd a nd d a t a to the dev i ce to perform the cle a r i ng of the ppb lock b i t . the p ass word is 64 bi t s long, s o the us er m us t wr i te the p ass word unlock comm a nd 2 t i me s for a x 3 2 bi t d a t a bus a nd 4 t i me s for a x16 d a t a bus. a0 is us ed to determ i ne whether the 3 2 bi t d a t a qua nt i ty is us ed to m a tch the u pper 3 2 bi t s or lower 3 2 bi t s. a0 a nd a -1 is us ed for m a tch i ng when the x16 bi t d a t a bus is s e-
june 7, 2006 am29bdd160g 43 lected (word# = 0) . wr i t i ng the p ass word unlock comm a nd is a ddre ss order s pec i f i c . in other word s , for the x 3 2 d a t a bus conf i g u r a t i on, the lower 3 2 bi t s of the p ass word a re wr i tten f i r s t a nd then the u pper 3 2 bi t s of the p ass word a re wr i tten . for the x16 d a t a bus conf i g- u r a t i on, the lower a ddre ss a0 : a -1 = 00, the next p ass - word unlock comm a nd is to a0 : a -1 = 01, then to a0 : a -1 = 10, a nd f i n a lly to a0 : a -1 = 11 . wr i t i ng o u t of s e- qu ence re su lt s i n the p ass word unlock not ret u rn i ng a m a tch w i th the p ass word a nd the ppb lock b i t re- m ai n s s et . once the p ass word unlock comm a nd is entered, the rdy/b s y# p i n goe s low i nd i c a t i ng th a t the dev i ce is bus y . al s o, re a d i ng the s m a ll ba nk (25 % ba nk) re su lt s i n the dq6 p i n toggl i ng, i nd i c a t i ng th a t the p ass word unlock f u nct i on is i n progre ss. re a d i ng the l a rge ba nk (75 % ba nk) ret u rn s a ct ua l a rr a y d a t a. approx i m a tely 1 us ec is re qui red for e a ch port i on of the u nlock . once the f i r s t port i on of the p ass word u nlock complete s (rdy/b s y# is not dr i ven a nd dq6 doe s not toggle when re a d), the p ass word unlock comm a nd is issu ed a g ai n, only th is t i me w i th the next p a rt of the p ass - word . if word# = 1, the s econd p ass word unlock comm a nd is the f i n a l comm a nd b efore the ppb lock b i t is cle a red ( assu m i ng a v a l i d p ass word) . if word# = 0, th is is the fo u rth p ass word unlock comm a nd . in x16 mode, fo u r p ass word unlock comm a nd s a re re- qui red to su cce ss f u lly cle a r the ppb lock b i t . a s w i th the f i r s t p ass word unlock comm a nd, the ry/by# si g- n a l goe s low a nd re a d i ng the dev i ce re su lt s i n the dq6 p i n toggl i ng on su cce ssi ve re a d oper a t i on s u nt i l complete . it is the re s pon sibi l i ty of the m i croproce ss or to keep tr a ck of the n u m b er of p ass word unlock com- m a nd s (2 for x 3 2 bus a nd 4 for x16 bus ), the order, a nd when to re a d the ppb lock bi t to conf i rm su c- ce ss f u l p ass word u nlock the p ass word unlock comm a nd is perm i tted i f the s ec si s ector is en ab led . ppb pro g ram command the ppb progr a m comm a nd is us ed to progr a m, or s et, a g i ven ppb . e a ch ppb is i nd i v i d ua lly pro- gr a mmed ( bu t is bu lk er as ed w i th the other ppb s ) . the s pec i f i c s ector a ddre ss (a1 8 ?a11) a re wr i tten a t the sa me t i me as the progr a m comm a nd 60h w i th a6 = 0 . if the ppb lock b i t is s et a nd the corre s pond i ng ppb is s et for the s ector, the ppb progr a m comm a nd w i ll not exec u te a nd the comm a nd w i ll t i me-o u t w i tho u t progr a mm i ng the ppb . the ho s t s y s tem m us t determ i ne whether a ppb h as b een f u lly progr a mmed b y not i ng the s t a t us of dq0 i n the si xth cycle of the ppb progr a m comm a nd . if dq0 = 0, the ent i re si x-cycle ppb progr a m comm a nd s e- qu ence m us t b e re issu ed u nt i l dq0 = 1 . all ppb era s e command the all ppb er as e comm a nd is us ed to er as e a ll ppb s i n bu lk . there is no me a n s for i nd i v i d ua lly er as - i ng a s pec i f i c ppb . unl i ke the ppb progr a m, no s pe- c i f i c s ector a ddre ss is re qui red . however, when the ppb er as e comm a nd is wr i tten (60h) a nd a6 = 1, a ll s ector ppb s a re er as ed i n p a r a llel . if the ppb lock b i t is s et the all ppb er as e comm a nd w i ll not exec u te a nd the comm a nd w i ll t i me-o u t w i tho u t er asi ng the ppb s. the ho s t s y s tem m us t determ i ne whether a ll ppb h as b een f u lly er as ed b y not i ng the s t a t us of dq0 i n the si xth cycle of the all ppb er as e comm a nd . if dq0 = 1, the ent i re si x-cycle all ppb er as e comm a nd s e qu ence m us t b e re issu ed u nt i l dq0 = 1 . it is the re s pon sibi l i ty of the us er to preprogr a m a ll ppb s pr i or to issui ng the all ppb er as e comm a nd . if the us er a ttempt s to er as e a cle a red ppb, over-er a - su re m a y occ u r m a k i ng i t d i ff i c u lt to progr a m the ppb a t a l a ter t i me . al s o note th a t the tot a l n u m b er of ppb progr a m/er as e cycle s is l i m i ted to 100 cycle s. cycl i ng the ppb s b eyond 100 cycle s is not g ua r a nteed . the all ppb er as e comm a nd is perm i tted i f the s ec si s ector is en ab led . dyb wr i te the dyb wr i te comm a nd is us ed for s ett i ng the dyb, wh i ch is a vol a t i le bi t th a t is cle a red a t re s et . there is one dyb per s ector . if the ppb is s et, the s ector is protected reg a rdle ss of the v a l u e of the dyb . if the ppb is cle a red, s ett i ng the dyb to a 1 protect s the s ector from progr a m s or er as e s. si nce th is is a vol a t i le bi t, remov i ng power or re s ett i ng the dev i ce w i ll cle a r the dyb s. the ba nk a ddre ss is l a tched when the com- m a nd is wr i tten . the dyb wr i te comm a nd is perm i tted i f the s ec si s ector is en ab led . ppb lock b i t s et the ppb lock b i t s et comm a nd is us ed for s ett i ng the dyb, wh i ch is a vol a t i le bi t th a t is cle a red a t re s et . there is one dyb per s ector . if the ppb is s et, the s ector is protected reg a rdle ss of the v a l u e of the dyb . if the ppb is cle a red, s ett i ng the dyb to a 1 protect s the s ector from progr a m s or er as e s. si nce th is is a vol- a t i le bi t, remov i ng power or re s ett i ng the dev i ce w i ll cle a r the dyb s. the ba nk a ddre ss is l a tched when the comm a nd is wr i tten . the ppb lock comm a nd is perm i tted i f the s ec si s ec- tor is en ab led . dyb s tatu s the progr a mm i ng of the dyb for a g i ven s ector c a n b e ver i f i ed b y wr i t i ng a dyb s t a t us ver i fy comm a nd to the dev i ce .
44 am29bdd160g june 7, 2006 ppb s tatu s the progr a mm i ng of the ppb for a g i ven s ector c a n b e ver i f i ed b y wr i t i ng a ppb s t a t us ver i fy comm a nd to the dev i ce . ppb lock b i t s tatu s the progr a mm i ng of the ppb lock b i t for a g i ven s ec- tor c a n b e ver i f i ed b y wr i t i ng a ppb lock b i t s t a t us ver i fy comm a nd to the dev i ce . non-volat i le protect i on b i t pro g ram and era s e flow the dev i ce us e s a s t a nd a rd comm a nd s e qu ence for progr a mm i ng or er asi ng the s ec si s ector protect i on, p ass word lock i ng, per sis tent s ector protect i on mode lock i ng, or per sis tent protect i on b i t s. unl i ke dev i ce s th a t h a ve the si ngle h i gh volt a ge s ector unpro- tect/protect fe a t u re, the am2 9 bdd160 h as the s t a n- d a rd two-cycle u nlock followed b y 60h, wh i ch pl a ce s the dev i ce i nto non-vol a t i le bi t progr a m or er as e mode . once the mode is entered, the s pec i f i c non-vol a t i le bi t s t a t us is re a d on dq0 . f i g u re 4 s how s a typ i c a l flow for progr a mm i ng the non-vol a t i le bi t a nd f i g u re 5 s how s a typ i c a l flow for er asi ng the non-vol a t i le bi t s. the s ec si s ector protect i on, p ass word lock i ng, per- sis tent s ector protect i on mode lock i ng bi t s a re not era s able a fter they a re progr a mmed . however, the ppb s a re b oth er asab le a nd progr a mm ab le (depend- i ng u pon dev i ce s ec u r i ty) . unl i ke si ngle h i gh volt a ge s ector protect/unprotect, the a6 p i n no longer f u nct i on s as the progr a m/er as e s elector nor the progr a m/er as e m a rg i n en ab le . in- s te a d, th is f u nct i on is a ccompl is hed b y issui ng the s pec i f i c comm a nd for e i ther progr a m (6 8 h) or er as e (60h) . in as ynchrono us mode, the dq6 toggle bi t i nd i c a te s whether the progr a m or er as e s e qu ence is a ct i ve . (in s ynchrono us mode, adv# i nd i c a te s the s t a t us. ) if the dq6 toggle bi t toggle s w i th e i ther oe# or ce#, the non-vol a t i le bi t progr a m or er as e oper a t i on is i n progre ss. when dq6 s top s toggl i ng, the v a l u e of the non-vol a t i le bi t is a v ai l ab le on dq0 .
june 7, 2006 am29bdd160g 45 legend: ba = addre ss of the ba nk th a t is b e i ng s w i tched to au to s elect mode, is i n b yp ass mode, or is b e i ng er as ed . determ i ned b y a18 a nd a17, s ee t ab le s 11 a nd 12 for more det ai l . pa = progr a m addre ss (a18 : a0) . addre ss e s l a tch on the f a ll i ng edge of the we# or ce# p u l s e, wh i chever h a ppen s l a ter . pd = progr a m d a t a (dq31 : dq0) wr i tten to loc a t i on pa . d a t a l a tche s on the r isi ng edge of we# or ce# p u l s e, wh i chever h a ppen s f i r s t . ra = re a d addre ss (a18 : a0) . rd = re a d d a t a (dq31 : dq0) from loc a t i on ra . sa = sector addre ss (a18 : a11) for ver i fy i ng ( i n au to s elect mode), er asi ng, or a pply i ng s ec u r i ty comm a nd s. wd = wr i te d a t a. see ?conf i g u r a t i on reg is ter? def i n i t i on for s pec i f i c wr i te d a t a. d a t a l a tched on r isi ng edge of we# . x = don?t c a re notes: 1 . see t ab le 1 for de s cr i pt i on of bus oper a t i on s. 2 . all v a l u e s a re i n hex a dec i m a l . 3 . sh a ded cell s i n t ab le denote re a d cycle s. all other cycle s a re wr i te oper a t i on s. 4 . d u r i ng u nlock cycle s , (lower a ddre ss bi t s a re 555 or 2aah as s hown i n t ab le) a ddre ss bi t s h i gher th a n a11 (except where ba is re qui red) a nd d a t a bi t s h i gher th a n dq7 a re don?t c a re s. 5 . no u nlock or comm a nd cycle s re qui red when ba nk is re a d i ng a rr a y d a t a. 6 . the re s et comm a nd is re qui red to ret u rn to the re a d mode (or to the er as e- sus pend-re a d mode i f prev i o us ly i n er as e s us pend) when a ba nk is i n the au to s elect mode, or i f dq5 goe s h i gh (wh i le the ba nk is prov i d i ng s t a t us i nform a t i on) . 7 . the fo u rth cycle of the au to s elect comm a nd s e qu ence is a re a d cycle . the s y s tem m us t prov i de the ba nk a ddre ss to o b t ai n the m a n u f a ct u rer id or dev i ce id i nform a t i on . see the a u to s elect comm a nd s ect i on for more i nform a t i on . 8 . th is comm a nd c a nnot b e exec u ted u nt i l the unlock byp ass comm a nd m us t b e exec u ted b efore wr i t i ng th is comm a nd s e qu ence . the unlock byp ass re s et comm a nd m us t b e exec u ted to ret u rn to norm a l oper a t i on . 9 . th is comm a nd is i gnored d u r i ng a ny em b edded progr a m, er as e or sus pended oper a t i on . 10 . v a l i d re a d oper a t i on s i ncl u de as ynchrono us a nd bu r s t re a d mode oper a t i on s. 11 . the dev i ce id m us t b e re a d a cro ss the fo u rth, f i fth, a nd si xth cycle s. 00h i n the si xth cycle i nd i c a te s top b oot b lock, 01h i nd i c a te s b ottom b oot b lock . 12 . the s y s tem m a y re a d a nd progr a m i n non-er asi ng s ector s , or enter the au to s elect mode, when i n the progr a m/er as e s us pend mode . the progr a m/er as e s us pend comm a nd is v a l i d only d u r i ng a s ector er as e oper a t i on, a nd re qui re s the ba nk a ddre ss. 13 . the progr a m/er as e re su me comm a nd is v a l i d only d u r i ng the er as e s us pend mode, a nd re qui re s the ba nk a ddre ss. 14 . comm a nd is v a l i d when dev i ce is re a dy to re a d a rr a y d a t a or when dev i ce is i n au to s elect mode . 15 . a s ynchrono us re a d oper a t i on s. 16 . acc m us t b e a t v id d u r i ng the ent i re oper a t i on of th is comm a nd . 17 . comm a nd is i gnored d u r i ng a ny em b edded progr a m, em b edded er as e, or s us pend oper a t i on . 18 . the unlock byp ass entry comm a nd is re qui red pr i or to a ny unlock byp ass oper a t i on . the unlock byp ass re s et comm a nd is re qui red to ret u rn to the re a d mode . table 19 . memory array command def i n i t i on s (x 3 2 mode) command (note s ) cycle s bu s cycle s (note s 1?4) f i r s t s econd th i rd fourth f i fth si xth addr data addr data addr data addr data addr data addr data re a d (5) 1 ra rd re s et (6) 1 xxx f0 a u to s elect (7) m a n u f a ct u rer id 4 555 aa 2aa 55 555 9 0 (ba)x00 01 dev i ce id (11) 6 555 aa 2aa 55 555 9 0 (ba)x01 7e (ba)x0e 0 8 (ba)x0f 00/01 progr a m 4 555 aa 2aa 55 555 a0 pa pd ch i p er as e 6 555 aa 2aa 55 555 8 0 555 aa 2aa 55 555 10 s ector er as e 6 555 aa 2aa 55 555 8 0 555 aa 2aa 55 s a 3 0 progr a m/er as e sus pend (12) 1 ba b0 progr a m/er as e re su me (1 3 )1ba 3 0 cfi q u ery (14, 15) 1 55 98 acceler a ted progr a m (16) 2 xx a0 pa pd conf i g u r a t i on reg is ter ver i fy (15) 3 555 aa 2aa 55 (ba)555 c6 (ba)xx rd conf i g u r a t i on reg is ter wr i te (17) 4 555 aa 2aa 55 555 d0 xx wd unlock byp ass entry (1 8 ) 3 555 aa 2aa 55 555 20 unlock byp ass progr a m (1 8 ) 2 xx a0 pa pd unlock byp ass er as e (1 8 )2xx 8 0xx10 unlock byp ass cfi (14, 1 8 )1xx 98 unlock byp ass re s et (1 8 )2xx 9 0xx00
46 am29bdd160g june 7, 2006 dyb = dyn a m i c protect i on b i t ow = addre ss (a5?a0) is (011x10) . ppb = per sis tent protect i on b i t pwa = p ass word addre ss. a0 s elect s b etween the low a nd h i gh 32- bi t port i on s of the 64- bi t p ass word pwd = p ass word d a t a. m us t b e wr i tten over two cycle s. pl = p ass word protect i on mode lock addre ss (a5?a0) is (001x10) rd(0) = re a d d a t a dq0 protect i on i nd i c a tor bi t . if protected, dq0= 1, i f u nprotected, dq0 = 0 . rd(1) = re a d d a t a dq1 protect i on i nd i c a tor bi t . if protected, dq1 = 1, i f u nprotected, dq1 = 0 . sa = sector addre ss where s ec u r i ty comm a nd a ppl i e s. addre ss bi t s a18 : a11 u n iqu ely s elect a ny s ector . sl = per sis tent protect i on mode lock addre ss (a5?a0) is (010x10) wp = ppb addre ss (a5?a0) is (111x10) x = don?t c a re ppmlb = p ass word protect i on mode lock i ng b i t spmlb = per sis tent protect i on mode lock i ng b i t 1 . see t ab le 1 for de s cr i pt i on of bus oper a t i on s. 2 . all v a l u e s a re i n hex a dec i m a l . 3 . sh a ded cell s i n t ab le denote re a d cycle s. all other cycle s a re wr i te oper a t i on s. 4 . d u r i ng u nlock cycle s , (lower a ddre ss bi t s a re 555 or 2aah as s hown i n t ab le) a ddre ss bi t s h i gher th a n a11 (except where ba is re qui red) a nd d a t a bi t s h i gher th a n dq7 a re don?t c a re s. 5 . the re s et comm a nd ret u rn s the dev i ce to re a d i ng the a rr a y . 6 . the fo u rth cycle progr a m s the a ddre ss ed lock i ng bi t . the f i fth a nd si xth cycle s a re us ed to v a l i d a te whether the bi t h as b een f u lly progr a mmed . if dq0 ( i n the si xth cycle) re a d s 0, the progr a m comm a nd m us t b e issu ed a nd ver i f i ed a g ai n . 7 . d a t a is l a tched on the r isi ng edge of we# . 8 . the ent i re fo u r bus -cycle s e qu ence m us t b e entered for e a ch port i on of the p ass word . 9 . the fo u rth cycle er as e s a ll ppb s. the f i fth a nd si xth cycle s a re us ed to v a l i d a te whether the bi t s h a ve b een f u lly er as ed . if dq0 ( i n the si xth cycle) re a d s 1, the er as e comm a nd m us t b e issu ed a nd ver i f i ed a g ai n . 10 . before issui ng the er as e comm a nd, a ll ppb s s ho u ld b e progr a mmed i n order to prevent over-er asu re of ppb s. 11 . in the fo u rth cycle, 00h i nd i c a te s ppb s et; 01h i nd i c a te s ppb not s et . 12 . the s t a t us of a dd i t i on a l ppb s a nd dyb s m a y b e re a d (follow i ng the fo u rth cycle) w i tho u t re issui ng the ent i re comm a nd s e qu ence . table 20 .s ector protect i on command def i n i t i on s (x 3 2 mode) command (note s ) cycle s bu s cycle s (note s 1-4) f i r s t s econd th i rd fourth f i fth si xth addr data addr data addr data addr data addr data addr data re s et 1 xxx f0 s ec si s ector entry 3 555 aa 2aa 55 555 88 s ec si s ector ex i t 4 555 aa 2aa 55 555 9 0xx 00 s ec si protect i on b i t progr a m (5, 6) 6 555 aa 2aa 55 555 60 ow 6 8 ow 4 8 ow rd(0) s ec si protect i on b i t s t a t us 6 555 aa 2aa 55 555 60 ow rd(0) p ass word progr a m (5, 7, 8 ) 4 555 aa 2aa 55 555 38 pwa[0-1] pwd[0-1] p ass word ver i fy 4 555 aa 2aa 55 555 c 8 pwa[0-1] pwd[0-1] p ass word unlock (7, 8 ) 5 555 aa 2aa 55 555 2 8 pwa[0-1] pwd[0-1] ppb progr a m (5, 6) 6 555 aa 2aa 55 555 60 ( s a)wp 6 8 ( s a)wp 4 8 ( s a)wp rd(0) all ppb er as e (5, 9 , 10) 6 555 aa 2aa 55 555 60 wp 60 ( s a)wp 40 ( s a)wp rd(0) ppb s t a t us (11, 12) 4 555 aa 2aa 55 555 9 0( s a)x02 00/01 ppb lock b i t s et 3 555 aa 2aa 55 555 7 8 ppb lock b i t s t a t us 4 555 aa 2aa 55 (ba) 555 5 8 s a rd(1) dyb wr i te (7) 4 555 aa 2aa 55 555 4 8s ax1 dyb er as e (7) 4 555 aa 2aa 55 555 4 8s ax0 dyb s t a t us (12) 4 555 aa 2aa 55 (ba) 555 5 8 s a rd(0) ppmlb progr a m (5,6) 6 555 aa 2aa 55 555 60 pl 6 8 pl 4 8 pl rd(0) ppmlb s t a t us (5) 6 555 aa 2aa 55 555 60 pl rd(0) s pmlb progr a m (5, 6) 6 555 aa 2aa 55 555 60 s l6 8s l4 8 s l rd(0) s pmlb s t a t us (5) 6 555 aa 2aa 55 555 60 s l rd(0)
june 7, 2006 am29bdd160g 47 table 21 . memory array command def i n i t i on s (x16 mode) legend: ba = addre ss of the ba nk th a t is b e i ng s w i tched to au to s elect mode, is i n b yp ass mode, or is b e i ng er as ed . determ i ned b y a18 a nd a17, s ee t ab le s 11 a nd 12 for more det ai l . pa = progr a m addre ss (a18 : a-1) . addre ss e s l a tch on the f a ll i ng edge of the we# or ce# p u l s e, wh i chever h a ppen s l a ter . pd = progr a m d a t a (dq15 : dq0) wr i tten to loc a t i on pa . d a t a l a tche s on the r isi ng edge of we# or ce# p u l s e, wh i chever h a ppen s f i r s t . ra = re a d addre ss (a18 : a-1) . rd = re a d d a t a (dq15 : dq0) from loc a t i on ra . sa = sector addre ss (a18 : a11) for ver i fy i ng ( i n au to s elect mode), er asi ng, or a pply i ng s ec u r i ty comm a nd s. wd = wr i te d a t a. see ?conf i g u r a t i on reg is ter? def i n i t i on for s pec i f i c wr i te d a t a. d a t a l a tched on r isi ng edge of we# . x = don?t c a re notes: 1 . see t ab le 1 for de s cr i pt i on of bus oper a t i on s. 2 . all v a l u e s a re i n hex a dec i m a l . 3 . sh a ded cell s i n t ab le denote re a d cycle s. all other cycle s a re wr i te oper a t i on s. 4 . d u r i ng u nlock cycle s , (lower a ddre ss bi t s a re aaa or 555h as s hown i n t ab le) a ddre ss bi t s h i gher th a n a11 (except where ba is re qui red) a nd d a t a bi t s h i gher th a n dq7 a re don?t c a re s. 5 . no u nlock or comm a nd cycle s re qui red when ba nk is re a d i ng a rr a y d a t a. 6 . the re s et comm a nd is re qui red to ret u rn to the re a d mode (or to the er as e- sus pend-re a d mode i f prev i o us ly i n er as e s us pend) when a ba nk is i n the au to s elect mode, or i f dq5 goe s h i gh (wh i le the ba nk is prov i d i ng s t a t us i nform a t i on) . 7 . the fo u rth cycle of the au to s elect comm a nd s e qu ence is a re a d cycle . the s y s tem m us t prov i de the ba nk a ddre ss to o b t ai n the m a n u f a ct u rer id or dev i ce id i nform a t i on . see the a u to s elect comm a nd s ect i on for more i nform a t i on . 8 . th is comm a nd c a nnot b e exec u ted u nt i l the unlock byp ass comm a nd m us t b e exec u ted b efore wr i t i ng th is comm a nd s e qu ence . the unlock byp ass re s et comm a nd m us t b e exec u ted to ret u rn to norm a l oper a t i on . 9 . th is comm a nd is i gnored d u r i ng a ny em b edded progr a m, er as e or sus pended oper a t i on . 10 . v a l i d re a d oper a t i on s i ncl u de as ynchrono us a nd bu r s t re a d mode oper a t i on s. 11 . the dev i ce id m us t b e re a d a cro ss the fo u rth, f i fth, a nd si xth cycle s. 00h i n the si xth cycle i nd i c a te s top b oot b lock, 01h i nd i c a te s b ottom b oot b lock . 12 . the s y s tem m a y re a d a nd progr a m i n non-er asi ng s ector s , or enter the au to s elect mode, when i n the progr a m/er as e s us pend mode . the progr a m/er as e s us pend comm a nd is v a l i d only d u r i ng a s ector er as e oper a t i on, a nd re qui re s the ba nk a ddre ss. 13 . the progr a m/er as e re su me comm a nd is v a l i d only d u r i ng the er as e s us pend mode, a nd re qui re s the ba nk a ddre ss. 14 . comm a nd is v a l i d when dev i ce is re a dy to re a d a rr a y d a t a or when dev i ce is i n au to s elect mode . 15 . a s ynchrono us re a d oper a t i on s. 16 . acc m us t b e a t v id d u r i ng the ent i re oper a t i on of th is comm a nd . 17 . comm a nd is i gnored d u r i ng a ny em b edded progr a m, em b edded er as e, or s us pend oper a t i on . 18 . the unlock byp ass entry comm a nd is re qui red pr i or to a ny unlock byp ass oper a t i on . the unlock byp ass re s et comm a nd is re qui red to ret u rn to the re a d mode . command (note s ) cycle s bu s cycle s (note s 1?4) f i r s t s econd th i rd fourth f i fth si xth addr data addr data addr data addr data addr data addr data re a d (5) 1 ra rd re s et (6) 1 xxx f0 a u to s elect (7) m a n u f a ct u rer id 4 aaa aa 555 55 aaa 9 0 (ba)x00 01 dev i ce id (11) 6 aaa aa 555 55 aaa 9 0 (ba)x02 7e (ba)x1c 0 8 (ba)x1e 00/01 progr a m 4 aaa aa 555 55 aaa a0 pa pd ch i p er as e 6 aaa aa 555 55 aaa 8 0 aaa aa 555 55 555 10 s ector er as e 6 aaa aa 555 55 aaa 8 0 aaa aa 555 55 s a 3 0 progr a m/er as e sus pend (12) 1 ba b0 progr a m/er as e re su me (1 3 )1ba 3 0 cfi q u ery (14, 15) 1 aa 98 acceler a ted progr a m (16) 2 xx a0 pa pd conf i g u r a t i on reg is ter ver i fy (15) 3 aaa aa 555 55 (ba)555 c6 (ba)xx rd conf i g u r a t i on reg is ter wr i te (17) 4 aaa aa 555 55 aaa d0 xx wd unlock byp ass entry (1 8 ) 3 aaa aa 555 55 aaa 20 unlock byp ass progr a m (1 8 ) 2 xx a0 pa pd unlock byp ass er as e (1 8 )2xx 8 0xx10 unlock byp ass cfi (14, 1 8 )1xx 98 unlock byp ass re s et (1 8 )2xx 9 0xx00
48 am29bdd160g june 7, 2006 legend: dyb = dyn a m i c protect i on b i t ow = addre ss (a5?a0) is (011x10) . pd3 : 0 = fo u r 32- bi t qua nt i t i e s repre s ent i ng the p ass word . ppb = per sis tent protect i on b i t pwa = p ass word addre ss. a0 : a-1 s elect s b etween the low a nd h i gh 16- bi t port i on s of the 64- bi t p ass word pwd = p ass word d a t a. m us t b e wr i tten over fo u r cycle s. pl = p ass word protect i on mode lock addre ss (a5-a0) is (001x10) rd(0) = re a d d a t a dq0 protect i on i nd i c a tor bi t . if protected, dq0 = 1, i f u nprotected, dq0 = 0 . rd(1) = re a d d a t a dq1 protect i on i nd i c a tor bi t . if protected, dq1 = 1, i f u nprotected, dq1 = 0 . sa = sector addre ss where s ec u r i ty comm a nd a ppl i e s. addre ss bi t s a18 : a11 u n iqu ely s elect a ny s ector . sl = per sis tent protect i on mode lock addre ss (a5?a0) is (010x10) wp = ppb addre ss (a5?a0) is (111x10) x = don?t c a re ppmlb = p ass word protect i on mode lock i ng b i t spmlb = per sis tent protect i on mode lock i ng b i t 1 . see t ab le 1 for de s cr i pt i on of bus oper a t i on s. 2 . all v a l u e s a re i n hex a dec i m a l . 3 . sh a ded cell s i n t ab le denote re a d cycle s. all other cycle s a re wr i te oper a t i on s. 4 . d u r i ng u nlock cycle s , (lower a ddre ss bi t s a re aaa or 555h as s hown i n t ab le) a ddre ss bi t s h i gher th a n a11 (except where ba is re qui red) a nd d a t a bi t s h i gher th a n dq7 a re don?t c a re s. 5 . the re s et comm a nd ret u rn s the dev i ce to re a d i ng the a rr a y . 6 . the fo u rth cycle progr a m s the a ddre ss ed lock i ng bi t . the f i fth a nd si xth cycle s a re us ed to v a l i d a te whether the bi t h as b een f u lly progr a mmed . if dq0 ( i n the si xth cycle) re a d s 0, the progr a m comm a nd m us t b e issu ed a nd ver i f i ed a g ai n . 7 . d a t a is l a tched on the r isi ng edge of we# . 8 . the ent i re fo u r bus -cycle s e qu ence m us t b e entered for e a ch port i on of the p ass word . pwa[0?3] repre s ent the fo u r a ddre ss e s over wh i ch the p ass word is s tored . pwd[0?3] repre s ent the fo u r word d a t a th a t compr is e the p ass word . 9 . the fo u rth cycle er as e s a ll ppb s. the f i fth a nd si xth cycle s a re us ed to v a l i d a te whether the bi t s h a ve b een f u lly er as ed . if dq0 ( i n the si xth cycle) re a d s 1, the er as e comm a nd m us t b e issu ed a nd ver i f i ed a g ai n . 10 . before issui ng the er as e comm a nd, a ll ppb s s ho u ld b e progr a mmed i n order to prevent over-er asu re of ppb s. 11 . in the fo u rth cycle, 00h i nd i c a te s ppb s et; 01h i nd i c a te s ppb not s et . 12 . the s t a t us of a dd i t i on a l ppb s a nd dyb s m a y b e re a d (follow i ng the fo u rth cycle) w i tho u t re issui ng the ent i re comm a nd s e qu ence . table 22 .s ector protect i on command def i n i t i on s (x16 mode) command (note s ) cycle s bu s cycle s (note s 1-4) f i r s t s econd th i rd fourth f i fth si xth addr data addr data addr data addr data addr data addr data re s et 1 xxx f0 s ec si s ector entry 3 aaa aa 555 55 aaa 88 s ec si s ector ex i t 4 aaa aa 555 55 aaa 9 0xx 00 s ec si protect i on b i t progr a m (5, 6) 6 aaa aa 555 55 aaa 60 ow 6 8 ow 4 8 ow rd(0) s ec si protect i on b i t s t a t us 6 aaa aa 555 55 aaa 60 ow rd(0) p ass word progr a m (5, 7, 8 ) 5 aaa aa 555 55 aaa 38 pwa[0? 3 ] pwd[0? 3 ] p ass word ver i fy 4 aaa aa 555 55 aaa c 8 pwa[0? 3 ] pwd[0? 3 ] p ass word unlock (7, 8 ) 5 aaa aa 555 55 aaa 2 8 pwa[0? 3 ] pwd[0? 3 ] ppb progr a m (5, 6) 6 aaa aa 555 55 aaa 60 ( s a)wp 6 8 ( s a)wp 4 8 ( s a)wp rd(0) all ppb er as e (5, 9 , 10) 6 aaa aa 555 55 aaa 60 wp 60 ( s a)wp 40 ( s a)wp rd(0) ppb s t a t us (11, 12) 4 aaa aa 555 55 aaa 9 0( s a)x04 00/01 ppb lock b i t s et 3 aaa aa 555 55 aaa 7 8 ppb lock b i t s t a t us 4 aaa aa 555 55 (ba) aaa 5 8 s a rd(1) dyb wr i te (7) 4 aaa aa 555 55 aaa 4 8s ax1 dyb er as e (7) 4 aaa aa 555 55 aaa 4 8s ax0 dyb s t a t us (12) 4 aaa aa 555 55 (ba) aaa 5 8 s a rd(0) ppmlb progr a m (5, 6) 6 aaa aa 555 55 aaa 60 pl 6 8 pl 4 8 pl rd(0) ppmlb s t a t us (5) 6 aaa aa 555 55 aaa 60 pl rd(0) s pmlb progr a m (5, 6) 6 aaa aa 555 55 aaa 60 s l6 8s l4 8 s l rd(0) s pmlb s t a t us (5) 6 aaa aa 555 55 aaa 60 s l rd(0)
june 7, 2006 am29bdd160g 49 write operation s tatu s the dev i ce prov i de s s ever a l bi t s to determ i ne the s t a - t us of a wr i te oper a t i on : dq2, dq 3 , dq5, dq6, dq7, a nd ry/by# . t ab le 2 3 a nd the follow i ng subs ect i on s de s cr ib e the f u nct i on s of the s e bi t s. dq7, ry/by#, a nd dq6 e a ch offer a method for determ i n i ng whether a progr a m or er as e oper a t i on is complete or i n progre ss. the s e three bi t s a re d is c uss ed f i r s t . dq7: data# poll i n g the am2 9 bdd160 fe a t u re s a d a t a # poll i ng fl a g as a method to i nd i c a te to the ho s t s y s tem whether the em- b edded a lgor i thm s a re i n progre ss or a re complete . d u r i ng the em b edded progr a m algor i thm a n a ttempt to re a d the ba nk i n wh i ch progr a mm i ng w as i n i t ia ted w i ll prod u ce the complement of the d a t a l as t wr i tten to dq7 . upon complet i on of the em b edded progr a m al- gor i thm, a n a ttempt to re a d the dev i ce w i ll prod u ce the tr u e l as t d a t a wr i tten to dq7 . note th a t data# poll i ng ret u rn s i nv a l i d d a t a for the a ddre ss b e i ng progr a mmed or er as ed . for ex a mple, the d a t a re a d for a n a ddre ss pro- gr a mmed as 0000 0000 1000 0000 b w i ll ret u rn xxxx xxxx 0xxx xxxx b d u r i ng a n em b edded progr a m oper a t i on . once the em b edded progr a m algor i thm is complete, the tr u e d a t a is re a d ba ck on dq7 . note th a t a t the i n s t a nt when dq7 s w i tche s to tr u e d a t a , the other bi t s m a y not yet b e tr u e . however, they w i ll a ll b e tr u e d a t a on the next re a d from the dev i ce . ple as e note th a t d a t a # poll i ng m a y g i ve m is le a d i ng s t a t us when a n a ttempt is m a de to wr i te to a protected s ec- tor . for ch i p er as e, the d a t a # poll i ng fl a g is v a l i d a fter the r isi ng edge of the si xth we# p u l s e i n the si x wr i te p u l s e s e qu ence . for s ector er as e, the d a t a # poll i ng is v a l i d a fter the l as t r isi ng edge of the s ector er as e we# p u l s e . d a t a # poll i ng m us t b e performed a t s ector a d- dre ss e s w i th i n a ny of the s ector s b e i ng er as ed a nd not a s ector th a t is a protected s ector . otherw is e, the s t a - t us m a y not b e v a l i d . dq7 = 0 d u r i ng a n em b edded er as e algor i thm (ch i p er as e or s ector er as e oper a t i on) bu t w i ll ret u rn a ?1? a fter the oper a t i on complete s b e- c aus e i t w i ll h a ve dropped ba ck i nto re a d mode . in as ynchrono us mode, jus t pr i or to the complet i on of the em b edded algor i thm oper a t i on s , dq7 m a y ch a nge as ynchrono us ly wh i le oe# is ass erted low . (in s ynchrono us mode, adv# exh ibi t s th is b eh a v i or . ) the s t a t us i nform a t i on m a y b e i nv a l i d d u r i ng the i n s t a nce of tr a n si t i on from s t a t us i nform a t i on to a rr a y (memory) d a t a. an extr a v a l i d i ty check is therefore s pec i f i ed i n the d a t a poll i ng a lgor i thm . the v a l i d a rr a y d a t a on dq 3 1?dq0 (dq15?dq0 when word# = 0) is a v ai l- ab le for re a d i ng on the next su cce ssi ve re a d a ttempt . the d a t a # poll i ng fe a t u re is only a ct i ve d u r i ng the em- b edded progr a mm i ng algor i thm, em b edded er as e al- gor i thm, er as e sus pend, er as e sus pend-progr a m mode, or s ector er as e t i me-o u t . if the us er a ttempt s to wr i te to a protected s ector, d a t a # poll i ng w i ll b e a ct i v a ted for ab o u t 1 s: the de- v i ce w i ll then ret u rn to re a d mode, w i th the d a t a from the protected s ector u nch a nged . if the us er a ttempt s to er as e a protected s ector, toggle b i t (dq6) w i ll b e a ct i v a ted for ab o u t 150 s; the dev i ce w i ll then ret u rn to re a d mode, w i tho u t h a v i ng er as ed the protected s ector . t ab le 2 3 s how s the o u tp u t s for d a t a # poll i ng on dq7 . f i g u re 6 s how s the d a t a # poll i ng a lgor i thm . f i g u re 27 s how s the t i m i ng d ia gr a m for s ynchrono us s t a t us dq7 d a t a poll i ng . ry/by#: ready/bu s y# the dev i ce prov i de s a ry/by# open dr ai n o u tp u t p i n as a w a y to i nd i c a te to the ho s t s y s tem th a t the em b edded algor i thm s a re e i ther i n progre ss or h a ve b een com- pleted . if the o u tp u t is low, the dev i ce is bus y w i th e i ther a progr a m, er as e, or re s et oper a t i on . if the o u tp u t is flo a t i ng, the dev i ce is re a dy to a ccept a ny re a d/wr i te or er as e oper a t i on . when the ry/by# p i n is low, the de- v i ce w i ll not a ccept a ny a dd i t i on a l progr a m or er as e comm a nd s w i th the except i on of the er as e sus pend comm a nd . if the dev i ce h as entered er as e sus pend mode, the ry/by# o u tp u t w i ll b e flo a t i ng . for progr a m- m i ng, the ry/by# is v a l i d (ry/by# = 0) a fter the r isi ng edge of the fo u rth we# p u l s e i n the fo u r wr i te p u l s e s e- qu ence . for ch i p er as e, the ry/by# is v a l i d a fter the r isi ng edge of the si xth we# p u l s e i n the si x wr i te p u l s e s e qu ence . for s ector er as e, the ry/by# is a l s o v a l i d a fter the r isi ng edge of the si xth we# p u l s e . if re s et# is ass erted d u r i ng a progr a m or er as e oper- a t i on, the ry/by# p i n rem ai n s a ?0? ( bus y) u nt i l the i n- tern a l re s et oper a t i on is complete, wh i ch re qui re s a t i me of t ready (d u r i ng em b edded algor i thm s ) . the s y s - tem c a n th us mon i tor ry/by# to determ i ne whether the re s et oper a t i on is complete . if re s et# is ass erted when a progr a m or er as e oper a t i on is not exec u t i ng (ry/by# p i n is ?flo a t i ng?), the re s et oper a t i on is com- pleted i n a t i me of t ready (not d u r i ng em b edded algo- r i thm s ) . the s y s tem c a n re a d d a t a t rh a fter the re s et# p i n ret u rn s to v ih . si nce the ry/by# p i n is a n open-dr ai n o u tp u t, s ever a l ry/by# p i n s c a n b e t i ed together i n p a r a llel w i th a p u ll- u p re sis tor to v cc . an extern a l p u ll- u p re sis tor is re- qui red to t a ke ry/by# to a v ih level si nce the o u tp u t is a n open dr ai n . t ab le 2 3 s how s the o u tp u t s for ry/by# . f i g u re s 15, 1 9 , 21 a nd 22 s how s ry/by# for re a d, re s et, progr a m, a nd er as e oper a t i on s , re s pect i vely .
50 am29bdd160g june 7, 2006 dq6: to gg le b i t i toggle b i t i on dq6 i nd i c a te s whether a n em b edded progr a m or er as e a lgor i thm is i n progre ss or complete, or whether the dev i ce h as entered the er as e sus pend mode . toggle b i t i m a y b e re a d a t a ny a ddre ss , a nd is v a l i d a fter the r isi ng edge of the f i n a l we# p u l s e i n the comm a nd s e qu ence (pr i or to the progr a m or er as e op- er a t i on), a nd d u r i ng the s ector er as e t i me-o u t . d u r i ng a n em b edded progr a m or er as e a lgor i thm op- er a t i on, two i mmed ia tely con s ec u t i ve re a d cycle s to a ny a ddre ss c aus e dq6 to toggle . when the oper a t i on is complete, dq6 s top s toggl i ng . for as ynchrono us mode, e i ther oe# or ce# c a n b e us ed to control the re a d cycle s. for s ynchrono us mode, the r isi ng edge of adv# is us ed or the r isi ng edge of clock wh i le adv# is low . after a n er as e comm a nd s e qu ence is wr i tten, i f a ll s ec- tor s s elected for er asi ng a re protected, dq6 toggle s for a pprox i m a tely 100 s , then ret u rn s to re a d i ng a rr a y d a t a. if not a ll s elected s ector s a re protected, the em- b edded er as e a lgor i thm er as e s the u nprotected s ec- tor s , a nd i gnore s the s elected s ector s th a t a re protected . the s y s tem c a n us e dq6 a nd dq2 together to deter- m i ne whether a s ector is a ct i vely er asi ng or is er as e- sus pended . when the dev i ce is a ct i vely er asi ng (th a t is , the em b edded er as e a lgor i thm is i n progre ss ), dq6 toggle s. when the dev i ce enter s the er as e sus - pend mode, dq6 s top s toggl i ng . however, the s y s tem m us t a l s o us e dq2 to determ i ne wh i ch s ector s a re er asi ng or er as e- sus pended . altern a t i vely, the s y s tem c a n us e dq7 ( s ee the subs ect i on on dq7 : d a t a # poll- i ng ) . if a progr a m a ddre ss f a ll s w i th i n a protected s ector, dq6 toggle s for a pprox i m a tely 1 s a fter the progr a m comm a nd s e qu ence is wr i tten, then ret u rn s to re a d i ng a rr a y d a t a. dq6 a l s o toggle s d u r i ng the er as e- sus pend-progr a m mode, a nd s top s toggl i ng once the em b edded pro- gr a m a lgor i thm is complete . t ab le 2 3 s how s the o u tp u t s for toggle b i t i on dq6 . f i g u re 7 s how s the toggle bi t a lgor i thm i n flowch a rt form, a nd the s ect i on re a d i ng toggle b i t s dq6/dq2 expl ai n s the a lgor i thm . f i g u re 25 i n the ac ch a r a cter- is t i c s s ect i on s how s the toggle bi t t i m i ng d ia gr a m s. f i g- u re 25 s how s the d i fference s b etween dq2 a nd dq6 i n gr a ph i c a l form . s ee a l s o the subs ect i on on dq2 : tog- gle b i t ii . f i g u re 27 s how s the t i m i ng d ia gr a m for s yn- chrono us toggle bi t s t a t us. dq2: to gg le b i t ii the ?toggle b i t ii? on dq2, when us ed w i th dq6, i nd i - c a te s whether a p a rt i c u l a r s ector is a ct i vely er asi ng (th a t is , the em b edded er as e a lgor i thm is i n progre ss ), or whether th a t s ector is er as e- sus pended . toggle b i t ii is v a l i d a fter the r isi ng edge of the f i n a l we# p u l s e i n the comm a nd s e qu ence . dq2 toggle s when the s y s tem perform s two i mmed i - a tely con s ec u t i ve re a d s a t a ddre ss e s w i th i n tho s e s ec- tor s th a t h a ve b een s elected for er asu re . (for as ynchrono us mode, e i ther oe# or ce# c a n b e us ed to control the re a d cycle s. for s ynchrono us mode, adv# is us ed . ) b u t dq2 c a nnot d is t i ng uis h whether dq7 = d a t a ? ye s no no dq5 = 1? no ye s ye s fail pa ss re a d dq7?dq0 addr = va re a d dq7?dq0 addr = va dq7 = d a t a ? s tart notes: 1 . va = v a l i d a ddre ss for progr a mm i ng . d u r i ng a s ector er as e oper a t i on, a v a l i d a ddre ss is a n a ddre ss w i th i n a ny s ector s elected for er asu re . d u r i ng ch i p er as e, a v a l i d a ddre ss is a ny non-protected s ector a ddre ss. 2 . dq7 s ho u ld b e rechecked even i f dq5 = ?1? b ec aus e dq7 m a y ch a nge si m u lt a neo us ly w i th dq5 . f ig ure 6 . data# poll i n g al g or i thm
june 7, 2006 am29bdd160g 51 the s ector is a ct i vely er asi ng or is er as e- sus pended . dq6, b y comp a r is on, i nd i c a te s whether the dev i ce is a ct i vely er asi ng, or is i n er as e sus pend, bu t c a nnot d is t i ng uis h wh i ch s ector s a re s elected for er asu re . th us , b oth s t a t us bi t s a re re qui red for s ector a nd mode i nform a t i on . refer to t ab le 2 3 to comp a re o u tp u t s for dq2 a nd dq6 . f i g u re 7 s how s the toggle bi t a lgor i thm i n flowch a rt form, a nd the s ect i on re a d i ng toggle b i t s dq6/dq2 expl ai n s the a lgor i thm . s ee a l s o the dq6 : toggle b i t i subs ect i on . f i g u re 25 s how s the toggle bi t t i m i ng d ia - gr a m . f i g u re 25 s how s the d i fference s b etween dq2 a nd dq6 i n gr a ph i c a l form . f i g u re 27 s how s the t i m i ng d ia gr a m for s ynchrono us dq2 toggle bi t s t a t us. read i n g to gg le b i t s dq6/dq2 refer to f i g u re 25 for the follow i ng d is c ussi on . when- ever the s y s tem i n i t ia lly b eg i n s re a d i ng toggle bi t s t a - t us , i t m us t perform two i mmed ia tely con s ec u t i ve re a d s of dq7?dq0 to determ i ne whether a toggle bi t is toggl i ng . typ i c a lly, the s y s tem wo u ld note a nd s tore the v a l u e of the toggle bi t a fter the f i r s t re a d . after the s econd re a d, the s y s tem wo u ld comp a re the new v a l u e of the toggle bi t w i th the f i r s t . if the toggle bi t is not toggl i ng, the dev i ce h as completed the progr a m or er as e oper a t i on . the s y s tem c a n re a d a rr a y d a t a on dq7?dq0 on the follow i ng re a d cycle . however, i f a fter the i n i t ia l two i mmed ia tely con s ec u t i ve re a d cycle s , the s y s tem determ i ne s th a t the toggle bi t is s t i ll toggl i ng, the s y s tem a l s o s ho u ld note whether the v a l u e of dq5 is h i gh ( s ee the s ect i on on dq5) . if i t is , the s y s tem s ho u ld then determ i ne a g ai n whether the toggle bi t is toggl i ng, si nce the toggle bi t m a y h a ve s topped toggl i ng jus t as dq5 went h i gh . if the toggle bi t is no longer toggl i ng, the dev i ce h as su cce ss f u lly com- pleted the progr a m or er as e oper a t i on . if i t is s t i ll tog- gl i ng, the dev i ce d i d not complete the oper a t i on su cce ss f u lly, a nd the s y s tem m us t wr i te the re s et com- m a nd to ret u rn to re a d i ng a rr a y d a t a. the rem ai n i ng s cen a r i o is th a t the s y s tem i n i t ia lly determ i ne s th a t the toggle bi t is toggl i ng a nd dq5 h as not gone h i gh . the s y s tem m a y cont i n u e to mon i tor the toggle bi t a nd dq5 thro u gh su cce ssi ve re a d cycle s , determ i n i ng the s t a t us as de s cr ib ed i n the prev i o us p a r a gr a ph . altern a t i vely, i t m a y choo s e to perform other s y s tem t as k s. in th is c as e, the s y s tem m us t s t a rt a t the b eg i nn i ng of the a lgor i thm when i t ret u rn s to determ i ne the s t a t us of the oper a t i on (top of f i g u re 7) . dq5: exceeded t i m i n g l i m i t s dq5 i nd i c a te s whether the progr a m or er as e t i me h as exceeded a s pec i f i ed i ntern a l p u l s e co u nt l i m i t . under the s e cond i t i on s dq5 prod u ce s a ?1 . ? th is is a f ai l u re cond i t i on th a t i nd i c a te s the progr a m or er as e cycle w as not su cce ss f u lly completed . the dq5 f ai l u re cond i t i on m a y a ppe a r i f the s y s tem tr i e s to progr a m a ?1? to a loc a t i on th a t is prev i o us ly progr a mmed to ?0 . ? only an era s e operat i on can chan g e a ?0? back to a ?1 . ? under th is cond i t i on, the dev i ce h a lt s the oper a t i on, a nd when the oper a t i on h as exceeded the t i m i ng l i m i t s , dq5 prod u ce s a ?1 . ? under b oth the s e cond i t i on s , the s y s tem m us t issu e the re s et comm a nd to ret u rn the dev i ce to re a d i ng a rr a y d a t a. s tart no ye s ye s dq5 = 1? no ye s dq6 = toggle? no re a d byte (dq0-dq7) addre ss = va dq6 = toggle? re a d byte tw i ce (dq 0-dq7) adrde ss = va re a d byte (dq0-dq7) addre ss = va fail pa ss n otes: 1 . re a d toggle bi t w i th two i mmed ia tely con s ec u t i ve re a d s to determ i ne whether or not i t is toggl i ng . see text . 2 . recheck toggle bi t b ec aus e i t m a y s top toggl i ng as dq5 ch a nge s to ?1? . see text . f ig ure 7 . to gg le b i t al g or i thm (note 1) (note s 1, 2)
52 am29bdd160g june 7, 2006 dq 3 : s ector era s e t i mer after wr i t i ng a s ector er as e comm a nd s e qu ence, the s y s tem m a y re a d dq 3 to determ i ne whether or not a n er as e oper a t i on h as b eg u n . (the s ector er as e t i mer doe s not a pply to the ch i p er as e comm a nd . ) if a dd i t i on a l s ector s a re s elected for er asu re, the ent i re t i me-o u t a l s o a ppl i e s a fter e a ch a dd i t i on a l s ector er as e comm a nd . when the t i me-o u t is complete, dq 3 s w i tche s from ?0? to ?1 . ? the s y s tem m a y i gnore dq 3 i f the s y s tem c a n g ua r a ntee th a t the t i me b etween a dd i t i on a l s ector er as e comm a nd s w i ll a lw a y s b e le ss th a n 50 s. s ee a l s o the s ector er as e comm a nd s ect i on . after the s ector er as e comm a nd s e qu ence is wr i tten, the s y s tem s ho u ld re a d the s t a t us on dq7 (d a t a # poll- i ng) or dq6 (toggle b i t i) to en su re the dev i ce h as a c- cepted the comm a nd s e qu ence, a nd then re a d dq 3. if dq 3 is ?1?, the i ntern a lly controlled er as e cycle h as b e- g u n ; a ll f u rther comm a nd s (other th a n er as e sus pend) a re i gnored u nt i l the er as e oper a t i on is complete . if dq 3 is ?0?, the dev i ce w i ll a ccept a dd i t i on a l s ector er as e comm a nd s. to e n su re the comm a nd h as b een a ccepted, the s y s tem s oftw a re s ho u ld check the s t a t us of dq 3 pr i or to a nd follow i ng e a ch subs e qu ent s ector er as e comm a nd . if dq 3 is h i gh on the s econd s t a t us check, the l as t comm a nd m i ght not h a ve b een a c- cepted . t ab le 2 3 s how s the o u tp u t s for dq 3. table 2 3. wr i te operat i on s tatu s notes: 1 . dq5 s w i tche s to ?1? when a n em b edded progr a m or em b edded er as e oper a t i on h as exceeded the m a x i m u m t i m i ng l i m i t s. see dq5 : exceeded t i m i ng l i m i t s for more i nform a t i on . 2 . dq7 a nd dq2 re qui re a v a l i d a ddre ss when re a d i ng s t a t us i nform a t i on . refer to the a ppropr ia te subs ect i on for f u rther det ai l s. operat i on dq7 (note 2) dq6 dq5 (note 1) dq 3 dq2 (note 2) ry/by# s t a nd a rd mode em b edded progr a m algor i thm dq7# toggle 0 n/a no toggle 0 em b edded er as e algor i thm 0 toggle 0 1 toggle 0 er as e sus pend mode re a d i ng w i th i n er as e sus pended s ector 1 no toggle 0 n/a toggle 1 re a d i ng w i th i n non-er as e sus pended s ector d a t a d a t a d a t a d a t a d a t a 1 er as e- sus pend-progr a m dq7# toggle 0 n/a n/a 0
june 7, 2006 am29bdd160g 53 absolute maximum ratings storage temperature plastic packages . . . . . . . . . . . . . . . ?65 c to +150 c ambient temperature with power applied. . . . . . . . . . . . . . ?55 c to +125 c v cc , v io (note 1) . . . . . . . . . . . . . . . .?0.5 v to +3.0 v acc, a9 , oe# , and reset# (note 2) . . . . . . . . . . . ?0.5 v to +13.0 v address, data, control signals (with the exception of clk (note 1) . .?0.5 v to +3.6 v all other pins (note 1) . . . . . . . . . . . . ?0.5 v to +5.5 v output short circuit current (note 3) . . . . . . 200 ma note s : 1. minimum dc voltage on input or i/o pins is ?0.5 v. during voltage transitions, input or i/o pins may overshoot v ss to ?0.7 v for periods of up to 20 ns. s ee figure 8 . maximum dc voltage on input or i/o pins is v cc +0.5 v. during voltage transitions, input or i/ o pins may overshoot to v cc +0.7 v for periods up to 20 ns. s ee figure 9 . 2. minimum dc input voltage on pins a 9 , oe#, and re s et# is ?0.5 v. during voltage transitions, a 9 , oe#, and re s et# may overshoot v ss to ?0.7 v for periods of up to 20 ns. s ee figure 8 . maximum dc input voltage on pin a 9 is +1 3 .0 v which may overshoot to 14.0 v for periods up to 20 ns. s ee figure 9 . 3 . no more than one output may be shorted to ground at a time. duration of the short circuit should not be greater than one second. 4. s tresses above those listed under ?absolute maximum ratings ? may cause permanent damage to the device. this is a stress rating only ; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. operating ranges industrial (i) devices ambient temperature (t a ) . . . . . . . . . ?40c to +85c extended (e) devices ambient temperature (t a ) . . . . . . . . ?40c to +125c v cc supply voltages v cc for all devices . . . . . . . . . . . . . . . . 2.5 v to 2.75 v v io supply voltages v io for all devices . . . . . . . . . . . . . . . . 1.65 v to 2.75 v note: operating ranges define those limits between which the functionality of t he device is guaranteed. 20 ns 20 ns +0.8 v ?0.5 v 20 ns ?0.7 v figure 8. maximum negative overshoot waveform 20 ns 20 ns v cc +0.7 v v cc +0.5 v 20 ns ?0.7 v figure 9. maximum positive overshoot waveform
54 am29bdd160g june 7, 2006 dc characteri s tic s cmo s compat i ble notes: 1 . the i cc c u rrent l is ted i ncl u de s b oth the dc oper a t i ng c u rrent a nd the fre qu ency dependent component . 2 . i cc a ct i ve wh i le em b edded er as e or em b edded progr a m is i n progre ss. 3 . not 100% te s ted . 4 . m a x i m u m i cc s pec i f i c a t i on s a re te s ted w i th v cc = v ccm a x . 5 . c u rrent m a x i m u m h as b een i ncre as ed si gn i f i c a ntly from d a t as heet rev isi on b+4, d a ted apr i l 8, 2003 . parameter de s cr i pt i on te s t cond i t i on s m i ntypmaxun i t i li inp u t lo a d c u rrent v in = v ss to v io , v io = v io m a x 1 . 0 a i liwp inp u t lo a d c u rrent, wp# v in = v ss to v io , v io = v io m a x ?25 a i lo o u tp u t le a k a ge c u rrent v out = v ss to v cc , v cc = v cc m a x 1 . 0 a i ccb v cc act i ve b u r s t re a d c u rrent (note 1) ce# = v il , oe# = v il 56 mhz 8 do ub le-word 70 9 0ma 66 mhz i cc1 v cc act i ve a s ynchrono us re a d c u rrent (note 1) ce# = v il ,oe# =v il 1 mhz 4 ma i cc 3 v cc act i ve progr a m c u rrent (note s 2, 4) ce# = v il ,oe# = v ih , acc = v ih 40 50 ma i cc4 v cc act i ve er as e c u rrent (note s 2, 4) ce# = v il ,oe# = v ih , acc = v ih 20 50 ma i cc5 (note 5) v cc s t a nd b y c u rrent (cmo s )v cc = v cc m a x , ce# = v cc 0 .3 v60 a i cc6 v cc act i ve c u rrent (re a d wh i le wr i te) ce# = v il ,oe# = v il 3 0 9 0ma i cc7 (note 5) v cc re s et c u rrent re s et# = v il 60 a i cc 8 (note 5) a u tom a t i c s leep mode c u rrent v ih = v cc 0 .3 v, v il = v ss 0 .3 v60 a i acc v acc acceler a t i on c u rrent acc = v hh 20 ma v il inp u t low volt a ge ?0 . 50 .3 x v io v v ih inp u t h i gh volt a ge 0 . 7 x v io 3. 6v v ilclk clk inp u t low volt a ge ?0 . 20 .3 x v io v v ihclk clk inp u t h i gh volt a ge 0 . 7 x v cc 2 . 75 v v id volt a ge for a u to s elect v cc = 2 . 5 v 11 . 512 . 5v v ol o u tp u t low volt a ge i ol = 4 . 0 ma, v cc = v cc m i n 0 . 45 v i olrb ry/by#, o u tp u t low c u rrent v ol = 0 . 4 v 8 ma v hh acceler a ted (acc p i n) h i gh volt a ge i oh = ?2 . 0 ma, v cc = v cc m i n 0 .8 5 x v cc v v oh o u tp u t h i gh volt a ge i oh = ?100 a, v cc = v cc m i n v io ?0 . 1v v lko low v cc lock-o u t volt a ge (note 3 )1 . 62 . 0v
june 7, 2006 am29bdd160g 55 dc characteri s tic s (cont i nued) zero power fla s h note: addre ss e s a re s w i tch i ng a t 1 mhz f ig ure 10 . i cc1 current v s. t i me ( s how i n g act i ve and automat i c s leep current s ) 5 4 3 2 1 0 0 500 1000 1500 2000 2500 3 000 3 500 4000 s upply current i n ma t i me i n n s 20 16 4 0 12 3 45 frequency i n mhz s upply current i n ma note: t = -40 c f ig ure 11 . typ i cal i cc1 v s. frequency 2 . 7 v 8 12
56 am29bdd160g june 7, 2006 te s t condition s table 24 . te s t s pec i f i cat i on s key to s witching waveform s s witching waveform s f ig ure 12 . te s t s etup note: d i ode s a re in3064 or e qui v a lent c l dev i ce under te s t te s t cond i t i on 54d, 64c 65a un i t o u tp u t lo a d 1 ttl g a te o u tp u t lo a d c a p a c i t a nce, c l ( i ncl u d i ng ji g c a p a c i t a nce) 3 0 100 pf inp u t r is e a nd f a ll t i me s 5n s inp u t p u l s e level s 0 . 0 v ? v io v inp u t t i m i ng me asu rement reference level s v io /2 v o u tp u t t i m i ng me asu rement reference level s v io /2 v k s 000010-pal waveform input s output s s te a dy ch a ng i ng from h to l ch a ng i ng from l to h don?t c a re, any ch a nge perm i tted ch a ng i ng, s t a te unknown doe s not apply center l i ne is h i gh imped a nce s t a te (h i gh z) v io v ss v io /2 v v io /2 v o u tp u t me asu rement level inp u t f ig ure 1 3. input waveform s and mea s urement level s
june 7, 2006 am29bdd160g 57 ac characteri s tic s v cc and v io power-up f ig ure 14 . v cc and v io power-up d i a g ram parameter de s cr i pt i on te s t s etup s peed un i t t vc s v cc s et u p t i me m i n50 s t vio s v io s et u p t i me m i n50 s t r s th re s et# low hold t i me m i n50 s v cc v iop re s et# t vc s t r s th t vio s
58 am29bdd160g june 7, 2006 ac characteri s tic s a s ynchronou s read operat i on s notes: 1 . not 100% te s ted . 2 . see f i g u re 12 a nd t ab le 24 for te s t s pec i f i c a t i on s parameter de s cr i pt i on te s t s etup s peed opt i on s un i t jedec s td . 54d 64c 65a t avav t rc re a d cycle t i me (note 1) m a x546467 n s t avqv t acc addre ss to o u tp u t del a y ce# = v il oe# = v il m a x546467 n s t elqv t ce ch i p en ab le to o u tp u t del a y oe# = v il m a x5 8 6 9 71 n s t glqv t oe o u tp u t en ab le to o u tp u t del a ym a x20 2 8 n s t ehqz t df ch i p en ab le to o u tp u t h i gh z (note 1) m a x10 n s t ghqz t df o u tp u t en ab le to o u tp u t h i gh z (note 1) m i n2 n s m a x10 n s t oeh o u tp u t en ab le hold t i me (note 1) re a dm i n0 n s toggle a nd d a t a # poll i ng m i n10 n s t axqx t oh o u tp u t hold t i me from addre ss e s , ce# or oe#, wh i chever occ u r s f i r s t (note 1) m i n2 n s
june 7, 2006 am29bdd160g 59 ac characteristics burst mode read note: s ee product s elector guide for minimum initial clock delay prior to initial valid data. t iacc may also be calculated using the following formula: t iacc = (clock delays) x (clock period) + t bacc . parameter description speed options unit jedec std. 54d 64c 65a t iacc asynchronous access time adv# valid clock to output delay (see note) max 54 64 67 ns t bacc burst access time valid clock to output delay max 9 fbga 9.5 pqfp 10 fbga 10 pqfp 17 ns t advcs adv# setup time to rising (falling) edge of clk min 4 5 7 ns t advch adv# hold time min 2 ns t advp adv# pulse width min 15 15 18 ns t bdh data hold time from next clock cycle max 4 ns t dvch valid data hold from clk min 2 3 3 ns t dind clk to valid ind/wait# max 9 fbga 9.5 pqfp 10 fbga 10 pqfp 17 ns t indh ind/wait# hold from clk min 2 3 3 ns t iacc clk to valid data out, initial burst access max 54 60 68 ns t clk clk period min 15 18 25 ns max 60 t cr clk rise time max 3 ns t cf clk fall time max 3 ns t ch clk high time min 2.5 2.5 3 ns t cl clk low time min 2.5 2.5 3 ns t ch ce# hold time min 3 ns t acs address setup time to clk (see note) min 5 6 7 ns t ach address hold time from adv# rising edge (see note) min 1 2 2 ns t oe output enable to output valid max 20 ns t df t oez output enable to output high z min 2 3 3 ns max 10 15 17 t ehqz t cez chip enable to output high z max 10 15 17 ns t ces ce# setup time to clock min 4 5 6 ns
60 am29bdd160g june 7, 2006 ac characteri s tic s f ig ure 15 . convent i onal read operat i on s t i m i n gs f ig ure 16 . bur s t mode read (x 3 2 mode) t ce o u tp u t s we# addre ss e s ce# oe# high z o u tp u t v a l i d high z addre ss e s s t ab le t rc t acc t oeh t oe 0 v ry/by# re s et# t df t oh da da + 2 da + 3 da + 31 oe#* dq0: dq31 a0: a18 aa ind# adv# clk ce# t ces t acs t advcs t advch t ach t oe t bacc t bdh t oez t cez t iacc da + 1
june 7, 2006 am29bdd160g 61 ac characteri s tic s f ig ure 17 . a s ynchronou s command wr i te t i m i n g note: all comm a nd s h a ve the sa me n u m b er of cycle s i n b oth as ynchrono us a nd s ynchrono us mode s , i ncl u d i ng the read/reset comm a nd . only a si ngle a rr a y a cce ss occ u r s a fter the f0h comm a nd is entered . all subs e qu ent a cce ss e s a re bu r s t mode when the bu r s t mode opt i on is en ab led i n the conf i g u r a t i on reg is ter . f ig ure 1 8. s ynchronou s command wr i te/read t i m i n g note: all comm a nd s h a ve the sa me n u m b er of cycle s i n b oth as ynchrono us a nd s ynchrono us mode s , i ncl u d i ng the read/reset comm a nd . only a si ngle a rr a y a cce ss occ u r s a fter the f0h comm a nd is entered . all subs e qu ent a cce ss e s a re bu r s t mode when the bu r s t mode opt i on is en ab led i n the conf i g u r a t i on reg is ter . adv# ce# v a l i d d a t a a1 8 - a0 dq 3 1 - dq0 we# oe# ind/wait# clk s t ab le addre ss t c s t ch t a s t ah t oeh t d s t dh t wph t wc t a s clk adv# d a t a in a1 8 - a0, word# dq 3 1 - dq0 oe# d a t a o u t v a l i d addre ss we# ind/wait# ce# v a l i d addre ss t d s t wp t ce s t advp t advc s t wck s t oe t ac s t ach t ac s t df t ehqz t dh t wadvh t advch 10 n s t ach t wc
62 am29bdd160g june 7, 2006 ac characteri s tic s hardware re s et (re s et#) note: not 100% te s ted . parameter de s cr i pt i on all s peed opt i on s jedec s td . te s t s etup un i t t ready re s et# p i n low (d u r i ng em b edded algor i thm s ) to re a d or wr i te ( s ee note) m a x11 s t ready re s et# p i n low (not d u r i ng em b edded algor i thm s ) to re a d or wr i te ( s ee note) m a x500 n s t rp re s et# p u l s e w i dth m i n500 n s t rh re s et# h i gh t i me before re a d ( s ee note) m i n50 n s t rpd re s et# low to s t a nd b y mode m i n20 s t rb ry/by# recovery t i me m i n0 n s t ready re s et# act i ve for b a nk not exec u t i ng em b edded algor i thm m a x500 n s t rh re s et# h i gh t i me b efore re a dm a x50 n s t ready re s et# act i ve for b a nk exec u t i ng em b edded algor i thm m a x11 s t drne re s et# del a y to re a d mode d u r i ng norm a l er as e m a x7 s t rmx re s et# del a y to re a d mode i f re s et# is held a ct i ve for m a x i m u m del a y ( s ee prev i o us two p a r a meter s ) m a x50 n s
june 7, 2006 am29bdd160g 63 ac characteri s tic s f ig ure 20 . wp# t i m i n g re s et# ry/by# ry/by# t rp t re a dy re s et t i m i n g to bank not execut i n g embedded al g or i thm t re a dy ce#, oe# t rh ce#, oe# re s et t i m i n g to bank execut i n g embedded al g or i thm re s et# t rp t rb f ig ure 19 . re s et# t i m i n gs progr a m/er as e comm a nd wp# dq 3 1 - dq0 v a l i d wp# t ch t d s t dh we# ry/by# t wpw s t wprh t wp
64 am29bdd160g june 7, 2006 ac characteri s tic s era s e/pro g ram operat i on s notes: 1 . not 100% te s ted . 2 . see the s ect i on for more i nform a t i on . parameter all s peed opt i on s jedec s td . de s cr i pt i on un i t t avav t wc wr i te cycle t i me (note 1) m i n60n s t avwl t a s addre ss s et u p t i me m i n0n s t wlax t ah addre ss hold t i me m i n25n s t dvwh t d s d a t a s et u p to we# r isi ng edge m i n15n s t whdx t dh d a t a hold from we# r isi ng edge m i n2n s t oe s o u tp u t en ab le s et u p t i me m i n0n s t ghwl t ghwl re a d recovery t i me before wr i te (oe# h i gh to we# low) m i n0n s t elwl t c s ce# s et u p t i me m i n0n s t wheh t ch ce# hold t i me m i n0n s ce# s et u p to clk m i n7 t wlwh t wp we# w i dth m i n25n s t whwl t wph wr i te p u l s e w i dth h i gh m i n 3 0n s t whwh1 t whwh1 progr a mm i ng oper a t i on (note 2) typ 9s t whwh2 t whwh2 s ector er as e oper a t i on (note 2) typ 0 . 5 s ec . t vc s v cc s et u p t i me (note 1) m i n50 s t rb recovery t i me from ry/by# m i n0n s t bu s y ry/by# del a y after we# r isi ng edge m a x 9 0n s t wpw s wp# s et u p to we# r isi ng edge w i th comm a nd m i n20n s t wprh wp# hold a fter ry/by# r isi ng edge m a x2 n s
june 7, 2006 am29bdd160g 65 ac characteri s tic s note: pa = progr a m a ddre ss , pd = progr a m d a t a , d out is the tr u e d a t a a t the progr a m a ddre ss. f ig ure 21 . pro g ram operat i on t i m i n gs oe# we# ce# v cc d a t a addre ss e s t d s t ah t dh t wp pd t whwh1 t wc t a s t wph t vc s 555h pa pa re a d s t a t us d a t a (l as t two cycle s ) a0h t c s s t a t us d out progr a m comm a nd s e qu ence (l as t two cycle s ) ry/by# t rb t bu s y t ch pa
66 am29bdd160g june 7, 2006 ac characteri s tic s note: sa = s ector a ddre ss (for sector er as e), va = v a l i d addre ss for re a d i ng s t a t us d a t a ( s ee wr i te oper a t i on st a t us ) . f ig ure 22 . ch i p/ s ector era s e operat i on t i m i n gs f ig ure 2 3. back-to-back cycle t i m i n gs oe# ce# addre ss e s v cc we# d a t a 2aah s a t ah t wp t wc t a s t wph 555h for ch i p er as e 10 for ch i p er as e 3 0h t d s t vc s t c s t dh 55h t ch in progre ss complete t whwh2 va va er as e comm a nd s e qu ence (l as t two cycle s )re a d s t a t us d a t a ry/by# t rb t bu s y oe# ce# we# addre ss e s t oh d a t a v a l i d in v a l i d in v a l i d pa v a l i d ra t wc t wph t ah t wp t d s t dh t rc t ce v a l i d o u t t oe t acc t oeh t ghwl t df v a l i d in ce# controlled wr i te cycle s we# controlled wr i te cycle v a l i d pa v a l i d pa t cp t cph t wc t wc re a d cycle t s r/w t wph
june 7, 2006 am29bdd160g 67 ac characteri s tic s we# ce# oe# h i gh z t oe h i gh z dq7 dq0?dq6 ry/by# t bu s y complement tr u e addre ss e s va t oeh t ce t ch t oh t df va va s t a t us d a t a complement s t a t us d a t a tr u e v a l i d d a t a v a l i d d a t a t acc t rc t wc note: va = v a l i d a ddre ss. ill us tr a t i on s how s f i r s t s t a t us cycle a fter comm a nd s e qu ence, l as t s t a t us re a d cycle, a nd a rr a y d a t a re a d cycle . f ig ure 24 . data# poll i n g t i m i n gs (dur i n g embedded al g or i thm s ) we# ce# oe# h i gh z t oe dq6/dq2 ry/by# t bu s y addre ss e s va t oeh t ce t ch t oh t df va va t acc t rc v a l i d d a t a v a l i d s t a t us v a l i d s t a t us (f i r s t re a d) ( s econd re a d) ( s top s toggl i ng) v a l i d s t a t us va note: va = v a l i d a ddre ss ; not re qui red for dq6 . ill us tr a t i on s how s f i r s t two s t a t us cycle a fter comm a nd s e qu ence, l as t s t a t us re a d cycle, a nd a rr a y d a t a re a d cycle . f ig ure 25 . to gg le b i t t i m i n gs (dur i n g embedded al g or i thm s )
68 am29bdd160g june 7, 2006 ac characteri s tic s note: the s y s tem m a y us e ce# or oe# to toggle dq2 a nd dq6 . dq2 toggle s only when re a d a t a n a ddre ss w i th i n a n er as e- sus pended s ector . f ig ure 26 . dq2 v s. dq6 for era s e and era s e s u s pend operat i on s enter er as e er as e er as e enter er as e sus pend progr a m er as e sus pend re a d er as e sus pend re a d er as e we# dq6 dq2 er as e complete er as e sus pend sus pend progr a m re su me em b edded er asi ng ce# clk avd# addre ss e s oe# d a t a rdy s t a t us d a t a s t a t us d a t a va va t oe t oe 1 . the t i m i ng s a re si m i l a r to s ynchrono us re a d t i m i ng s a nd as ynchrono us d a t a poll i ng t i m i ng s /toggle bi t t i m i ng . 2 . va = v a l i d addre ss. two re a d cycle s a re re qui red to determ i ne s t a t us. when the em b edded algor i thm oper a t i on is complete, the toggle bi t s w i ll s top toggl i ng . 3 . rdy is a ct i ve w i th d a t a (a18 = 0 i n the conf i g u r a t i on reg is ter) . when a18 = 1 i n the conf i g u r a t i on reg is ter, rdy is a ct i ve one clock cycle b efore d a t a. 4 . d a t a poll i ng re qui re s bu r s t a cce ss t i me del a y . f ig ure 27 .s ynchronou s data poll i n g t i m i n g /to gg le b i t t i m i n gs
june 7, 2006 am29bdd160g 69 sector protect: 150 s sector unprot ect: 15 ms 1 s reset# sa, a6, a1, a0 data ce# we# oe# 60h 60h/68h** 40h/48h*** valid* valid* valid* status sector protect/unprotect verify v ih * v a l i d a ddre ss for s ector protect : a6 = 0, a1 = 1, a0 = 0 . v a l i d a ddre ss for s ector u nprotect : a6 = 1, a1 = 1, a0 = 0 . ** comm a nd for s ector protect is 68h . comm a nd for s ector u nprotect is 60h . *** comm a nd for s ector protect ver i fy is 48h . comm a nd for s ector u nprotect ver i fy is 40h . f ig ure 2 8. s ector protect/unprotect t i m i n g d i a g ram
70 am29bdd160g june 7, 2006 ac characteri s tic s alternate ce# controlled era s e/pro g ram operat i on s notes: 1 . not 100% te s ted . 2 . see the s ect i on for more i nform a t i on . parameter all s peed opt i on s jedec s td . de s cr i pt i on un i t t avav t wc wr i te cycle t i me (note 1) m i n65n s t avel t a s addre ss s et u p t i me m i n0n s t elax t ah addre ss hold t i me m i n45n s t dveh t d s d a t a s et u p t i me m i n 3 5n s t ehdx t dh d a t a hold t i me m i n2n s t oe s o u tp u t en ab le s et u p t i me m i n0n s t ghel t ghel re a d recovery t i me before wr i te (oe# h i gh to we# low) m i n0n s t wlel t w s we# s et u p t i me m i n0n s t ehwh t wh we# hold t i me m i n0n s t wadv s we# r isi ng edge s et u p to adv# f a ll i ng edge m i n5n s t wp we# w i dth m i n15n s t wadvh we# f a ll i ng edge after adv# f a ll i ng edge m i n0n s t wck s we# r isi ng edge s et u p to clk r isi ng edge m i n5n s t eleh t cp ce# p u l s e w i dth m i n 3 5n s t ehel t cph ce# p u l s e w i dth h i gh m i n 3 0n s t whw s h1 t whwh1 progr a mm i ng oper a t i on (note 2) typ 9s t whwh2 t whwh2 s ector er as e oper a t i on (note 2) typ 0 . 5 s ec .
june 7, 2006 am29bdd160g 71 ac characteri s tic s t ghel t w s oe# ce# we# re s et# t d s d a t a t ah addre ss e s t dh t cp dq7# d out t wc t a s t cph pa d a t a # poll i ng a0 for progr a m 55 for er as e t rh t whwh1 or 2 ry/by# t wh pd for progr a m 3 0 for s ector er as e 10 for ch i p er as e 555 for progr a m 2aa for er as e pa for progr a m s a for s ector er as e 555 for ch i p er as e t bu s y t wph t wp notes: 1 . pa = progr a m a ddre ss , pd = progr a m d a t a , dq7# = complement of the d a t a wr i tten to the dev i ce, d out = d a t a wr i tten to the dev i ce . 2 . f i g u re i nd i c a te s the l as t two bus cycle s of the comm a nd s e qu ence . f ig ure 29 . alternate ce# controlled wr i te operat i on t i m i n gs
72 am29bdd160g june 7, 2006 era s e and programming performance notes: 1 . typ i c a l progr a m a nd er as e t i me s assu me the follow i ng cond i t i on s: 25 c, 2 . 5 v v cc , 1m cycle s. add i t i on a lly, progr a mm i ng typ i c a l s assu me checker b o a rd p a ttern . 2 . under wor s t c as e cond i t i on s of 145c, v cc = 2 . 5 v, 100,000 cycle s. 3 . the typ i c a l ch i p progr a mm i ng t i me is con si der ab ly le ss th a n the m a x i m u m ch i p progr a mm i ng t i me l is ted . 4 . in the pre-progr a mm i ng s tep of the em b edded er as e a lgor i thm, a ll b yte s a re progr a mmed to 00h b efore er asu re . 5 . sy s tem-level overhe a d is the t i me re qui red to exec u te the two- or fo u r- bus -cycle s e qu ence for the progr a m comm a nd . see t ab le s 19 a nd 20 for f u rther i nform a t i on on comm a nd def i n i t i on s. 6 . the dev i ce h as a m i n i m u m er as e a nd progr a m cycle end u r a nce of 1m cycle s. 7 . ppb s h a ve a m i n i m u m progr a m/er as e cycle end u r a nce of 100 cycle s. latchup characteri s tic s incl u de s a ll p i n s except v cc . te s t cond i t i on s: v cc = 3 . 0 v, one p i n a t a t i me . pqfp and fortified bga pin capacitance notes: 1 . s a mpled, not 100% te s ted . 2 . te s t cond i t i on s t a = 25c, f = 1 . 0 mhz . data retention parameter typ (note 1) max (note 2) un i t comment s s ector er as e t i me 1 . 05 s excl u de s 00h progr a mm i ng pr i or to er asu re (note 4) ch i p er as e t i me 2 3 2 3 0 s do ub le word progr a m t i me 1 8 250 s excl u de s s y s tem level overhe a d (note 5) word (x16) progr a m t i me 15 210 s acceler a ted do ub le word progr a m t i me 8 1 3 0 s acceler a ted ch i p progr a m t i me 5 50 s ch i p progr a m t i me (note 3 ) x16 10 100 s x 3 212120 de s cr i pt i on m i nmax inp u t volt a ge w i th re s pect to v ss on a ll p i n s except i/o p i n s ( i ncl u d i ng a 9 , acc, a nd wp#) ?1 . 0 v 12 . 5 v inp u t volt a ge w i th re s pect to v ss on a ll i/o p i n s ?1 . 0 v v cc + 1 . 0 v v cc c u rrent ?100 ma +100 ma parameter s ymbol parameter de s cr i pt i on te s t s etup typ max un i t c in inp u t c a p a c i t a nce v in = 0 6 7 . 5pf c out o u tp u t c a p a c i t a nce v out = 0 8. 512 pf c in2 control p i n c a p a c i t a nce v in = 0 7 . 5 9 pf parameter te s t cond i t i on s m i nun i t m i n i m u m p a ttern d a t a retent i on t i me 150 c10 ye a r s 125 c20 ye a r s
june 7, 2006 am29bdd160g 73 phy s ical dimen s ion s pqr0 8 0? 8 0-lead pla s t i c quad flat packa g e
74 am29bdd160g june 7, 2006 phy s ical dimen s ion s laa 0 8 0? 8 0-ball fort i f i ed ball gr i d array (1 3 x 11 mm)
june 7, 2006 am29bdd160g 75 revi s ion s ummary rev isi on b ( s eptember 3 0, 2002) in i t ia l p ub l i c rele as e . rev isi on b+1 (october 7, 2002) d is t i nct i ve character is t i c s ch a nged m a x i m u m power con su mpt i on on bu r s t mode re a d, progr a m/er as e oper a t i on s , a nd s t a nd b y mode . bur s t mode read table ch a nged t ce s s pec i f i c a t i on from 7, 8 , a nd 9 n s to 4, 5, a nd 6 n s , re s pect i vely . dc character is t i c s table deleted i cc2 s pec i f i c a t i on . ch a nged i ccb oe# te s t cond i t i on from v ih to v il . added 1 mhz te s t cond i t i on to i cc1 ; ch a nged oe# te s t cond i t i on from v ih to v il . ch a nged i cc 3 a nd i cc4 m a x i m u m v a l u e s a nd a dded typ i c a l v a l u e s. ch a nged m a x i m u m v a l u e s for i cc5 , i cc7 , a nd i cc 8 . added note 4 to t ab le . ac character is t i c s er as e a nd progr a m oper a t i on s t ab le : repl a ced tbd s for t ah a nd t wp w i th v a l u e s. era s e and pro g ramm i n g performance table repl a ced tbd s a nd ex is t i ng typ i c a l a nd m a x i m u m v a l- u e s w i th new v a l u e s. rev isi on b+2 (october 14, 2002) d is t i nct i ve character is t i c s , dc character is t i c s ch a nged v cc cmo s s t a nd b y c u rrent to 3 0 ma m a x . ab s olute max i mum rat i n gs ch a nged m a x i m u m r a t i ng for v cc to 3. 0 v . rev isi on b+ 3 (november 22, 2002) product s elector gu i de added a v ai l abi l i ty note . ch a nged m i n i m u m i n i t ia l clock del a y a nd m a x i m u m ce# a cce ss t i me on 54d, 65d, 64c, a nd 65a s peed s. ch a nged m a x i m u m oe# a c- ce ss t i me on 65a a nd 9 0a s peed s. order i n g informat i on added a v ai l abi l i ty note . s ee table 8 , bur s t in i t i al acce ss delay deleted def i n i t i on s a nd s ett i ng s col u mn s a nd a dded i n i t ia l bu r s t a cce ss col u mn s. f ig ure 3 , in i t i al bur s t delay control mod i f i ed dr a w i ng : deleted a rrow s connect i ng a d- dre ss /d a t a cycle s. deleted s ett i ng c a llo u t s. ch a nged n u m b er of del a y cycle s c a llo u t s. moved s t a rt of v a l i d addre ss cycle . fall i n g clk ed g e output and two-clk data hold deleted f i g u re . s ee table 9 , conf ig urat i on re gis ter def i n i t i on s mod i f i ed de s cr i pt i on s for cr 3 ?cr10 . s ee table 16 , cfi dev i ce geometry def i n i t i on mod i f i ed de s cr i pt i on of d a t a a t a ddre ss 2ch (x 3 2 mode) ; a dded d a t a 000 3 h . dc character is t i c s added m a x i m u m i cc6 s pec i f i c a t i on . ac character is t i c s a s ynchrono us re a d oper a t i on s: ch a nged t ce s pec i f i - c a t i on s for 54d, 65d, 64c, a nd 65a s peed opt i on s. ch a nged t df s pec i f i c a t i on s for 65a a nd 9 0a s peed op- t i on s. rev isi on b+4 (apr i l 8 , 200 3 ) d is t i nct i ve character is t i c s corrected typo i n si ngle power su pply oper a t i on . corrected typo i n perform a nce ch a r a cter is t i c s. product s elector gu i de upd a ted m a x b u r s t acce ss del a y for the 54d, 65d, 64c, a nd 8 0c s peed opt i on s. global removed reference s to i nterle a v i ng oper a t i on s thro u gho u t d a t as heet . table 6 . 16-b i t and 3 2-b i t l i near and interleaved bur s t data order removed 2nd row for ?fo u r interle a ved d a t a tr a n s - fer s ? a nd ?e i ght interle a ved d a t a tr a n s fer s ? . cont i nuou s bur s t read operat i on s , f ig ure 3. and f ig ure 4 . wa i t funct i on dur i n g cont i nuou s bur s t read s at wordl i ne boundary, f ig ure 5 . and f ig ure 6 . odd/even s tart i n g addre ss cont i nuou s bur s t mode al ig nment removed from d a t as heet . table 9 . conf ig urat i on re gis ter def i n i t i on s added ?re s erved? reference s to t ab le . s ector protect i on added s ector a nd s ector gro u p s ect i on .
76 am29bdd160g june 7, 2006 s ector era s e and pro g ram s u s pend operat i on mechan i c s added bu lleted s ect i on . ab s olute max i mum rat i n gs and operat i n g ran g e s added v io ch a nged 1 . 65 v to ?0 . 5 v ch a nged 2 .3 v to 2 . 5 v cmo s compat i ble removed ?v io ? from m a x col u mn of o u tp u t h i gh volt- a ge row . f ig ure 16 . bur s t mode read (x 3 2 mode) corrected typo s to subs cr i pt s. corrected v a l u e s for the t bacc a nd t dind for the 54d, 65d, 64c, a nd 8 0c s peed opt i on s. f ig ure 17 . a s ynchronou s command wr i te t i m i n g added t wc a nd t wph . f ig ure 1 8. s ynchronou s command wr i te/ read t i m i n g added t wc a nd t wph . hardware re s et (re s et#) corrected t ready m a x . f ig ure 20 . wp# wr i te t i m i n g added t wp . f ig ure 2 3. back-to-back cycle t i m i n gs added t wph . f ig ure 24 . data# poll i n g t i m i n gs (dur i n g embedded al g or i thm s ) added t wc . f ig ure 29 . alternate ce# controlled wr i te operat i on t i m i n gs added t wp a nd t wph era s e and pro g ramm i n g performance ch a nged the s ector er as e t i me typ i c a l to 1 . 0 . rev isi on b+5 (may 6, 200 3 ) global converted d a t a s heet from adv a nced inform a t i on to prel i m i n a ry . order i n g informat i on removed s ome opn s a nd m a rk i ng s. automat i c s leep mode (a s m) and s tandby mode reworded f i r s t p a r a gr a ph . dq7: data# poll i n g , dq6: to gg le b i t i and dq2: to gg le b i t ii added reference to f i g u re 27 . ab s olute max i mum rat i n gs added acc reference . cmo s compat i ble corrected m a x v a l u e s for the i cc5, 7, a nd 8 added note #5 . f ig ure 27 . s ynchronou s data poll i n g t i m i n gs /to gg le b i t t i m i n g added f i g u re . si multaneou s read/wr i te operat i on s overv i ew and re s tr i ct i on s added s ect i on s a nd t ab le . table 7 . bur s t in i t i al acce ss delay, table 8. conf ig urat i on re gis ter def i n i t i on s , table 2 3. te s t s pec i f i cat i on s , a s ynchronou s read operat i on s , and bur s t mode read removed the 65d, 8 0c, a nd 9 0a s peed opt i on s from t ab le s. rev isi on c (may 19, 200 3 ) no rev isi on s m a de, repo s t on we b. rev isi on c+1 (may 29, 200 3 ) d is t i nct i ve character is t i c s ch a nged the s t a nd b y mode to 60 a . product s elector gu i de ch a nged the s t a nd a rd volt a ge r a nge to 2 . 5-2 . 75 v output d is able mode repl a ce p a r a gr a ph . s ynchronou s (bur s t) read operat i on removed reference to ?cont i n u o us s e qu ent ia l? from s ect i on . f ig ure 3. in i t i al bur s t delay control ren u m b ered w a veform to re a d two, three, fo u r . to gg le b i t i added s entence to s econd p a r a gr a ph of s ect i on . cmo s compat i ble removed reference to cont i n u o us bu r s t from t ab le . bur s t mode read ch a nged the t iacc m a x for the 65a s peed opt i on to 67 n s.
june 7, 2006 am29bdd160g 77 figure 15. typical i cc1 vs. frequency renumbered supply current axis, removed 2.3 v graph, and changed other graph to 2.5 v. figure 27. synchronous data polling timing/toggle bit timings deleted line under the pulse in oe#. revision c+2 (june 26, 2003) product selector guide added note. synchronous (burst) read operation, adv#control in linear mode, and ind/wait# operation in linear mode removed feature. table. 7 valid configuration register bit definition for ind/wait# removed features. table 20. sector protection command definitions (x32 mode) changed the address for ow a5-a0 to 011x10. table 22. sector protection command definitions (x16 mode) changed the pwa sector to a0:a-1 figure 11. typical i cc1 vs. frequency changed 2.5 to 2.7 and made t= 40c burst mode read changed t bacc for 54d to 9 fbga and 9.5 pqfp. changed t dind for 54d to 9 fbga and 9.5 pqfp and for the 64c to 10 fbga and 10 pqfp. figure 27. synchronous data polling timing/toggle bit timing added note 4. revision d (june 30, 2003) global converted to a preliminary datasheet. revision d+1 (june 30, 2003) global removed ?preliminary ? status from data sheet. distinctive characteristics added temperature range to simultaneous read/write operations section. dc characteristics inserted i acc field to table. revision d2 (january 7, 2005) added note on cover page and first page of data sheet that the am29bdd160g has been superceded by the spansion s29cd016g. revision d3 (february 2, 2005) ordering information added lead free to package. added new package types to valid combinations. revision d4 (november 4, 2005) block diagram: changed ? dq0-dq15 to dq0-dq31 ? in the block diagram. connection diagram: restored labels to figure. absolute maximum ratings: changed voltages in vvershoot diagrams. ac characteristics, burst mode read table: deleted parameters t ds , t dh , t as , t ah , t cs revision d5 (june 7, 2006) global: restored previous formatting to document. trademarks copyright ? 2003?2006 advanced micro devices, inc. all rights reserved. amd, the amd logo, and combinations thereof are registered trademarks of advanced micro devices, inc. expressflash is a trademark of advanced micro devices, inc. product names used in this publication are for identification purposes only and may be trademarks of their respective companies .

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